MB87P2020 Datasheet, PDF (78/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
Main functionality is to provide an arbitrated video memory access for GDC components such as Pixel
Processor (PP), Direct/Indirect Memory Access (DIPA), the Video Interface Controller (VIC) and finally
the Graphic Processing Unit (GPU) which reads pixel data from memory and formats the output stream.
Because of the different requirements of the various components there are to support various access types,
such as burst and block modes with adjustable transfer sizes.
1.2 Arbitration
The arbitration of the four main GDC parts works priority based. The setup of priority values can be decided
by the requester component itself and is signalized to the SDRAM controller. The benefit is that the setup
can vary for different applications. There is also the possibility to change priority on the fly, e.g. if buffer
state changes. The connected component can decide about the urgency of the transfer.
Table 1-1: GDC modules and its priority registers with recommended configuration
Device
GPU
VIC
PP/AAF
DIPA
Register
Comment
SDCP_LP = 3
SDCP_HP = 7
low and high priority, real time device
with automatic priority scaling
SDRAM_LP = 2
SDRAM_HP = 6
low and high priority, real time device
with automatic priority scaling
SDCPRIO = 1
no automatic priority scaling sup-
ported
DIPACTRL_PDPA = 5 DIPACTRL_PIPA = 0 priorities for DPA and IPA access
Video RAM arbitration is done in principle of cooperative multitasking. This did not waste bandwidth if a
requester device uses only a part of its dedicated bandwidth as if time slicing would be used. All devices
share the commonly available bandwidth resource. Main advantage is that system performance could be
scaled and optimized for a wide range of different applications.
A decision about granting the next device is done priority based at the end of a currently processed device
request. The currently processed device is excluded from priority based selection for the next one. This re-
sults in granting requests for the two devices with given highest priorities alternately, if requested. Only
idling between these two devices could be used for the other ones. Therefore the devices with the two high-
est priorities could be considered as real-time (normally this should be GPU and VIC).
1.3 SDRAM Timing
Configurable options for the appropriate SDRAM timings listed in table 1-2. Defaults are listed for 100
MHz SDRAM types of MB811643242A for Lavender. Values for integrated DRAM version for Jasmine
are given in a separate column. The configuration value is a number of wait states. That means additional
Table 1-2: SDRAM Command Timings
Parameter
tRP (RAS Precharge
Time)
tRRD (RAS to RAS Bank
Active Delay Time
tRAS (RAS Active Time)
Default Jasmine
30 ns 22.5 ns
20 ns -
60 ns 37.5 ns
Description
Time from same bank PRE to row ACTV com-
mand
Time from ACTV to opposite bank ACTV com-
mand
Time from ACTV to same bank PRE command
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