MB87P2020 Datasheet, PDF (42/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
The ULB internal DMA controller is able to use all DMA modes supported by MB91360 series. It operates
together with input or output FIFO and uses programmable limits. In demand mode the controller calculates
the amount of data to transfer by its own. In other modes the programmer has to ensure that enough space
is available in input FIFO so that no data loss can occur.
Because of different clock frequencies for ULB bus and display controller core clock an important ULB
function is the data synchronisation between these two clock domains. A asynchronous interface is offered
by ULB which allows independent clocks for ULB and core as long as ULB clock is equal or slower than
core clock.
In order to adjust the display controller’s operation mode so called ’mode pins’ (MODE[3:0]) are used:
• The display controller can also act as an 16 Bit device from MCU’s point of view. In this case ULB con-
verts write data from 16 to 32 Bit and read data from 32 back to 16 Bit in order to hide interface param-
eters to internal display controller components. The data mode can be set by MODE[2].
• Up to four display controllers can join one chip select signal. So it is necessary to set the controller
’number’ by MODE[1:0]. ULB takes care about correct address decoding depending on this ’number’.
• In order to allow flexible PCB layout some signals can be inverted and can be set to tristate. For Jasmine
the inversion of ULB_RDY is controlled by MODE[3]. For more details about signal settings see
chapter 1.3.4.
In short terms the main functions of ULB are:
• MCU (User Logic Bus) bus control inclusive wait state handling for read access via ULB_RDY pin
• Address decoding and control of other display controller components
• Data buffering and synchronisation between different clock domains
• Command decoding and execution control
• Flag handling
• Programmable interrupt handling
• Programmable DMA based input/output FIFO control
• 16/32 Bit conversion for writing and reading
1.2 ULB overview
Figure 1-1 shows the block diagram of ULB top level design.
Table 1-1 gives an overview on main functions of ULB top level modules. Important modules will be ex-
plained in more detail in the following chapters.
Table 1-1: Top level modules of ULB
Name
Input Sync
Interrupt Controller (IC)
Address Decoder (AD)
Main functions
• Synchronization for write signals (MCU -> display controller)
• Flag register management
• Management of different interrupt sources
• User definable interrupt source masking and trigger condition
• Interrupt signal generation (Jasmine: programmable length for
edge request)
• Handling of other display controllers using the same chip select
signal
• Address decoding and calculation for direct SDRAM access
• Address segmentation management
• Control of MCU data I/O as result of address decoding
• Activation of Command Control, Register Control Unit (CTRL)
and Direct Physical Memory Access Units (DPA) as result of
address decoding
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