MB87P2020 Datasheet, PDF (21/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Graphic Controller Overview
3 Clock supply and generation
GDC has a flexible clocking concept where four input clocks (OSC_IN/OUT, DIS_PIXCLK, ULB_CLK,
RCLK) can be used as clock source for Core clock (CLKK) and Display clock (CLKD).
The user can choose by software whether to take the direct clock input or the output of an APLL independ-
ent for Core- and Display clock. Both output clocks have different dividers programmable by software
(DIV x for CLKD and DIV z for CLKK). The clock gearing facilities offer the possibility to scale system
performance and power consumption as needed.
OSC_IN/OUT
DIS_PIXCLK
ULB_CLK
RCLK
PLL Clock
APLL
MUL y
System Clock Prescaler
DIV z
CLKK
Direct Clock
Pixel Clock Prescaler
DIV x
invert option
CLKD
VSC_CLKV
Figure 3-1: Clock gearing and distribution
invert option
(Jasmine only)
CLKM
CLKV
Beside these two configurable clocks (CLKK and CLKD) GDC needs two additional internal clocks:
CLKM and CLKV (see also figure 3-1). CLKV is exclusively for video interface and is connected to input
clock pin VSC_CLKV. CLKM is used for User Logic Bus (ULB) interface and is connected to input clock
ULB_CLK. As already mentioned ULB_CLK can also be used to build CLKK and/or CLKD.
Table 3-1 shows all clocks used by GDC with their requirements.
Table 3-1: Clock supply
Clock
Type
Symbol
XTAL clock
input
OSC_IN, OSC_OUT
Requirements
Min
Typ Max
12^a
-
64
Reserve clock
ULB clock
Pixel clock
Video clock
Core clock
Display clock
Video clock
input
input
input
input
internal
internal
internal
RCLK
ULB_CLK
DIS_PIXCLK
VSC_CLKV
CLKK
CLKD
CLKV
ULB_CLK^{b -}
64
-
-
64
-
-
54
-
-
54^c
ULB_CLK -
64
-
-
54
-
-
54^c
ULB clock
internal CLKM
-
-
64
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Clock supply and generation
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