MB87P2020 Datasheet, PDF (297/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Register Description
Table 1-2: Register address space for Jasmine and Lavender
Register
Bits Group
Name Address
Name
Description
Default
value
SDWAIT
SDIF
SDCFLAG
PHA[16]
DSZ[16]
0x020C
20 OPT
19:16 TRP
15:12 TRRD
o
oo
o
11:8 TRAS
7:4 TRCD
3:0 TRW
oo
oo
oo
SDRAM timings (refer to
SDRAM manual)
Bank interleave optimization
RAS Precharge Time - 1
RAS to RAS Bank Active
Delay Time - 1
RAS Active Time - 1
RAS to CAS Delay Time - 1
Read to Write recovery time
Recommended values:
Lavender: 10 (8)^c
Jasmine: 7 (5)^c
0x0210
SDRAM port interface timing
(scalable clock delay) - is
ignored by Jasmine
7:6 TAO
o
Address output delay
5:4 TDO
o
Data output delay
3:2 TDI
o
Data sampling delay
1:0 TOE
o
Tristate control delay
0x0214
SDC control register
1
DQMEN
o
1: Enable DQM partial write
optimization
0
BUSY
oo
Set busy flag during micro-
program upload
GPU (Graphic Processing Unit)
GPU-LDR (Layer Description Record)
0x1000 -
0x103C
Physical layer address in
SDRAM
19:0 OFS
o
Address offset (RA, CA,
BYTE)
Bits[9:0] fixed to zero
22:0
o
Address offset (RA, BA, CA,
BYTE)
Bits[11:0] fixed to zero
0x1040 -
0x107C
29:16 o
oo
Layer domain size
o dimension of layer Size
1
0x2
1
0x5
0x2
0x3
Value for-
bidden!
Use recom-
mended val-
ues!
0
0
0
0
0
0
undef
undef
Register Description
Page 297