MB87P2020 Datasheet, PDF (206/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
6.4 Data Output
• GPU pixel output is always LSB-aligned, i.e. the geometrically leftmost pixel is represented in the
least significant bit(s). For cases where displays demand MSB-alignment this has to be produced by
appropriate wiring on the PCB. There are two exceptional cases: physical color space RGB111 and
bit stream format S4 or S8. Then fractions of a pixel are output and the alignment swap can not be
obtained by wiring only. Therefore, GPU provides the flag “R/B-swap” which exchanges the red
with the blue color channel (exchange of a pixel’s bit 0 and 2).
• Since GPU is designed for LCDs and equivalent progressive scan¹ display types it can not produce
TV-conform interlaced output streams. However, it can produce TV-conform timing signals (hsync
and vsync, cf. section 3.10) for displays which mimic TV behaviour.
• For bit stream formats other than S24 it is possible to control the values at the pins DIS_D[23:19]
directly by the user (aka port expansion mode). This is achieved by setting the respective sync mixer
signal selects all to constant zero. Then bit 0 of the mixer’s function table represents the pin value
directly. This direct control works for all bit stream formats on pins DIS_HSYNC, DIS_VSYNC,
and DIS_VREF, since these are always available.
• It is possible to run both, an analog and a digital display, concurrently with the same timing (only
valid for MB87P2020-A (Jasmine)). This is accomplished using the twin display mode (cf. 3.5).
However, this works only for single scan displays and pins DIS_D[23:19] may not be available for
sync signal output then.
6.5 Diagnostics
GPU provides some diagnostic information in read-only registers that might help during software develop-
ment. The following data are available:
• Current blink state (bits[31:16], register MDR_BlinkCtrl, address 0x1308). A ’1’ at a bit slice desig-
nates that the corresponding layer would use its alternative blink color. The information may be used
to synchronize different layers or to synchronize drawing and display. A simultaneous start of blink-
ing for all layers can be achieved by simultaneous setting of the blink enable bits (bits [15:0] of
MDR_BlinkCtrl).
• Current timing position (register DIR_TimingDiag, address 0x3024) in “timing coordinates” as
explained in section 3.9. The information is useful to check for correct register settings.
• Current input FIFO load (bits [15:8], register GPU_SDCPrio, address 0x3270). This information
allows to check for potential bandwidth bottlenecks. During normal operation the FIFO will be full
(load ≈ 130 ) most of the time. However, it does not constitute a critical state as such when it runs
empty. Only if there is not enough memory bandwidth left to refill it for longer periods of time the
LSA will consequently run empty and raise an interrupt.
1. The term progressive scan means that a complete frame is output line by line, whilst interlaced means that a
complete frame is output as two fields, where one field contains all lines with odd and the other field all lines
with even numbers.
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