MB87P2020 Datasheet, PDF (281/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

AC Characteristics
2.5.6 DMA Control Ports
For a functional description of GDC DMA controller and supported settings see User Logic Bus (ULB) con-
troller description. This specification describes only the physical timing of DMA control signals.
ULB_CLK
tHCSF
tSCSF
t HCSF
ULB_CS
t SWRX/RDX
tHWRX/RDX tSWRX/RDX tHWRX/RDX
ULB_RDX/WRX
t SA
tHA
ULB_A _{001100110011001100110011001100110011001100110011001100110011001100110011}
00110011001100110011001100110011001100110011001100110011
001100110011
t HDACK (Lav)
t HDACK (Jas)
t SDACK
ULB_DACK
ULB_DREQ
tODDREQ
tOHDREQ
00110011
Figure 2-6: DMA block/burst access
t RDREQ
tODDREQ
tOHDREQ
00110011
Table 2-11: DMA Timing Specification
Parameter
DMA acknowledge (ULB_DACK) Setup
Time (rising)
DMA acknowledge (ULB_DACK) Hold
Time (rising)^a
Symbol
t_SDACK
Min [ps]
Jas
Lav
-80
50
Max [ps]
Jas
Lav
-
t_HDACK
1600 -
-
DMA acknowledge (ULB_DACK) Hold
t_HDACK
-
Time (falling)^b
3130 -
DMA request (ULB_DREQ) Reaction Time t_RDREQ
1T / 3T^c
-
a. Jasmine has ULB_DACK timing requirement for rising clock edge only.
b. Lavender has ULB_DACK timing requirement to both edge types. DACK 1-> 0 transition only allowed
between falling and rising clock edge.
c. ULB_DREQ reaction time on ULB_DACK. 1 cycle in block/step/burst mode. Minimum 3 cycles in demand
mode.
Table 2-12: DMA Timing Specification, Output Characteristics
Parameter
max. DMA request (ULB_DREQ) Output
Delay Time
min. DMA request (ULB_DREQ) Output
Hold Time
Symbol
t_ODDREQ
t_OHDREQ
@20pF [ps]
Jas
Lav
14140 15480
@50pF [ps]
Jas
Lav
16170 17530
4200 4460 4600 4690
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