MB87P2020 Datasheet, PDF (67/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

User Logic Bus
FIFOSIZE
00110011001100110101
IFDMA_UL
IFDMA_LL
0
0000000000111111111100000000001111111111000000000011111111110000000000111111111100000000011111111101
Input FIFO
Output FIFO
Figure 1-17: FIFO limits for DMA transfer
description table in appendix. Figure 1-17 shows the meaning of these limits for input and output FIFO
while in table 1-14 the calculation for transfer sizes for FIFOs is listed.
In case of input FIFO the FIFO load has to be equal or smaller to meet trigger condition for DMA. For output
FIFO the load has to be equal or greater to trigger DMA transfer (see also figure 1-17).
Table 1-14: Transfer count calculation for DMA
Mode
Input FIFO
Output FIFO
Demand mode
trans = FIFOSIZE^a - FIFO load
trans = FIFO load
Block/step- or burst
mode
trans = <MCU defined>
trans = <MCU defined>
a. see table 1-10 for FIFO sizes for Lavender and Jasmine
Because the FIFOs can be accessed from GDC side (read from input FIFO and write to output FIFO) when
trigger condition becomes true the FIFO load itself is taken for calculation. In figure 1-17 this situation is
drawn.
IFDMA_LL ≤ FIFOSIZE – BLOCKSIZE ¹
(2)
OFDMA_UL ≥ BLOCKSIZE
(3)
For block/step- or burst mode condition (2) should be fulfilled for input FIFO in order to avoid FIFO over-
flow. For output FIFO at least one block should be available so that the condition (3) should be met. Oth-
erwise wrong data may be delivered because BLOCKSIZE is transfered at once and not all data are available
at transfer time.
For setup of DMA trigger levels the GDC internal packet sizes for data processing have to be considered.
This are IPA block transfers and REQCNT for pixel data packetizing in Pixel Processor. It depends on com-
mand how many words are read from input FIFO or written to output FIFO at once. The amount of data
words is determined by type of command data stream (address informations, colour data with different col-
our depths). See command description in appendix for a detailed command description.
In general the at once processed information must be available in IFIFO or has to fit into OFIFO. If this state
is not reached the execution devices wait for data transfer by MCU until the requirements are fulfilled. If
the DMA trigger levels are not set up accordingly deadlock situations can occur (data lack or jam).
1. BLOCKSIZE is the amount of words which is transfered at one DMA request (depends on MCU settings).
Functional description
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