MB87P2020 Datasheet, PDF (61/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

User Logic Bus
Additionally to flags inside flag register debug registers are implemented in Lavender and Jasmine in order
to watch command controller status. Table 1-12 lists these debug registers. Note that some registers are only
implemented in Jasmine.
Table 1-12: ULB debug registers
Register
Bits
Name
Description
Device
Name
Address
ULBDEB
7/6^a:0 ^IF
Current input FIFO load (command
independent)
all
0x0098 _15/14^a_:8 ^OF
Current output FIFO load
all
23/22^a:16 ^IFLC
Command dependent input FIFO
load
all
CMDDEB
0x009C
7:0
CMD
31:8 ^PAR
Currently executed command (see
chapter 1.5.3)
Command coded parameter for cur-
rent command (GetPA only)
Jasmine
Jasmine
a. Lavender/Jasmine value due to different FIFO sizes
1.6 Flag and interrupt handling
1.6.1 Flag and interrupt registers
The Interrupt Controller inside ULB contains one 32 Bit Flagregister (FLNOM; address 0x000C) and one
Interrupt-Mask-Register (INTNOM; address 0x0018) which allows a very flexible flag handling and inter-
rupt generation control.
In order to avoid data inconsistencies during bit masking within flag- or interrupt-mask-register the mask
process is implemented in hardware for these two registers. This helps to avoid flag changes by hardware
between a read and a write access (read->mask->write back).
To distinguish between set-, reset- and direct write access different addresses are used:
• Address (FLNOM, INTNOM): normal write operation
• Address + 4 (FLRST, INTRST): reset operation (1: reset flag on specified position, 0: don’t touch)
• Address + 8 (FLSET, INTSET): set operation (1: set flag on specified position; 0: don’t touch)
All of these three addresses write physically to one register with three different methods. For reading all
addresses return the value of the assigned register (FLNOM or INTNOM).
For writing all bus access types as described in chapter 1.4.4 are possible for each of these addresses.
1.6.2 Interrupt controller configuration
Figure 1-12 shows the basic structure of interrupt generation circuit for one flag.
The Flagregister itself is set and reset able by hard- or software. A set event by hard- or software sets the
flag to ’1’ and a reset event sets the flag to ’0’. Software flag access has a higher priority than hardware
events but hardware events may be present some clock cycles around software access which is only one
clock active after synchronisation.
Note: Despite the higher priority of software access the hardware event may overwrite
the software settings after MCU write access if the set- or reset condition for the
desired flag is still true.
Functional description
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