MB87P2020 Datasheet, PDF (91/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

SDRAM Controller
Assumed first pixel {0,0} address is searched for, physical address is Layer 0 start address directly.
PhyMap = GDC_CS_Area + WNDOF0 - WNDSD0 = 0x30000000 + 0x40000 - 0
PhyMap = 0x30040000
PhyAddr = PhyMap + PHA(0) = 0x30060000
Now for pixel position of Layer 0, X=115, Y= 250 physical address should be transformed.
RA = Y[13:6] * XRows + (X << Shift)[18:9]
RA = 250/64*20 + 115*16/512 = 3*20 + 1840/512 = 63 = 0x3f = 0b11 1111
BA = {Y[5], (X << Shift)[8]} = {bit 5 of 0xFA, bit 8 of 0x730} = 0b11
CA = {Y[4:0], (X << Shift)[7:5]} = {0b11010, 0b001} = 0b1101 0001
Con catenation of RA, BA and CA results in the physical SDRAM word address. Additional con catenation
of two bits 0b00 convert it to a byte address (x 4).
PhySDRAM = {RA, BA, CA, 0b00} = 0b11 1111. 11.11 0100 01.00 = 0x3FF44
Finally physical address offset for Layer 0 has to be added.
PhyAddr = 0x20000 + 0x3FF44 = 0x5FF44
This address can be used for IPA directly. For DPA GDC_CS_Area, WNDOF0 and WNDSD0 have to be
considered.
PhyAddrDPA = PhyMap + PhyAddr = 0x30040000 + 0x5FF44 = 0x3009FF44.
Function Description
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