MB87P2020 Datasheet, PDF (63/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

User Logic Bus
Jasmine contains an edge generation circuit which is responsible for a prolongation of an impulse in case
of an edge interrupt. The impulse length can be set in INTREQ_INTC within a range from 0 to 63 ULB
clocks. For every edge impulse at the input of the edge generation circuit a pulse with the programmed
length will be generated at output. If a level interrupt occurs the output signal follows the input signal syn-
chronized to ULB clock domain.
Lavender does not contain an edge generation circuit. Therefore no edge interrupt is possible.
For Lavender the default value for INTLVL register is edge trigger for interrupt for all flags. Make sure to
set the register INTLVL to 0x00000000 during Lavender initialisation.
For MCU interrupt programming ’H’ level should be used for display controller interrupt.
1.6.4 Interrupt configuration example
In figure 1-13 an example configuration for display controller and MCU is given. In this example an inter-
rupt should be activated when the input FIFO load is equal or lower than ’1’ (Register: G0IFUL). To acti-
vate the interrupt generation the Bit 3 of Interrupt-Mask-Register is set to ’1’ via the set address for this
register. The interrupt trigger for display controller is set to level.
For MCU first all interrupts are turned off, global interrupt level and level for GDC-interrupt is set, the
MCU interrupt trigger is also set to level to ensure a save detection. At the end the port for external interrupts
is enabled, pending interrupt requests will be deleted and interrupt execution is turned on again in order to
enable GDC interrupt execution. In MB91xxxx hardware manual the interrupt initialisation is described in
more detail.
;; ---------------------------------
;; Init GDC
writereg G0FLAGRES, 0x3f401fff; set FIFO flags to dynamic
writereg G0IFUL,
0x00000001; set input FIFO limits for interrupt
writereg G0INTLVL, 0x0 ; level triggered
writereg G0INTSET, 0x8 ; IF <= IF-low(=1)
;; ---------------------------------
;; Init MCU
andccr #0xef ; disable all interrupts
;; set interrupt level for ext. INT0
ldi
#0x14,r0; set interrupt level to 20
ldi
#ICR00, r1; load address for ext. INT0
stb
r0, @r1
;; set global interrupt level to 30
stilm #0x1e
;; initialize external interrupt
ldi
#0x1, r0; enable only INT0
ldi
#ENIR, r1; load address for int. enable register
stb
r0, @r1
;; set interrupt request level
ldi
#0b01, r0; set ’H’ level for INT0
ldi
#ELVR, r1; load address for external level register
sth
r0, @r1
;; enable interrupt ports
ldi
#0b00000001, r0; enable INT0
ldi
#PFRK, r1; port function register for interrupt 0
stb
r0, @r1
;; clear all interrupt requests
ldi
#0, r0
ldi
#EIRR, r1
stb
r0, @r1
nop
nop
nop
;; enable interrupts
orccr #0x10; set I-bit in CCR register
Functional description
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