MB87P2020 Datasheet, PDF (73/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

User Logic Bus
Table 2-1: ULB register description
Register
Name
Address
Bits Group
Name
Description
Default value
DSTP Duration of ULB_DSTP signal.
This value can be set in order to
12:8
ensure a save MCU-DMAC reset.
7
Normally the default value should
work.
TRI
’1’: Set ’1’ to tristate (’Z’) for
4
ULB_DREQ, ULB_DSTP and
0
INTRQ
DMAFLAG 0x0090
3 ^INV
’1’: Invert ULB_DREQ,
ULB_DSTP and INTRQ
0
MODE ’1’: DMA demand mode
2
’0’: DMA block/step- or burst
0
mode
1 EN
’1’: enable DMA
0
0 ^IO
’1’: use DMA for input FIFO
’0’: use DMA for output FIFO
1
FLAGRES
0x0094
-
31:0
’1’: set flag to dynamic behaviour^f
’0’: set flag to static behaviour^f
0x20400000
IFLC
23:16
Input FIFO load for current com-
mand
Attention: This value changes with
GDC core clock; correct sampling
by MCU can’t be ensured.
Value is read-only; writing is
ignored.
0x00
ULBDEB
OF
0x0098 15:8
Output FIFO load
Attention: This value changes with
GDC core clock; correct sampling
by MCU can’t be ensured.
Value is read-only; writing is
ignored.
0x00
IF
7:0
Input FIFO load independent from
current command
Attention: This value changes with
GDC core clock; correct sampling
by MCU can’t be ensured.
Value is read-only; writing is
ignored.
0x00
a. For meaning of flags and default value see section 1.6.
b. Attention: This is only allowed when GDC core clock is equal to ULB bus clock (see section 1.6)
c. See section 1.4.
d. IFLOAD: Input FIFO load
e. OFLOAD: Output FIFO load
f. For a description of flag handling see section 1.6.
ULB register set
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