MB87P2020 Datasheet, PDF (122/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
DPA with its single word accesses has normally not that important influence on system performance. The
granted access duration is very short. If the bandwidth requirements are not close to the edge, highest pri-
ority should be not problematic if assigned (i.e. DPA=7, GPU=6, VIC=5). If considered that bandwidth is
very critical for GPU or VIC a setting of GPU =7, VIC=6 and DPA=5 should be assigned.
IPA can lock the video RAM interface relative long time, even if a large maximum block size is specified.
Therefore a very low priority should be assigned to IPA, at least lower than the real-time devices GPU and
VIC. A low value did not necessarily reduce IPA performance. The data stream is buffered through the input
and output FIFOs. Only reaction time increases slightly for low priority requests. If bandwidth violations
occur for GPU or VIC at IPA usage at lowest priority, the maximum block transfer size should be reduced.
It may be possible that GPU FIFO under-run or VIC FIFO overflow occurs while IPA locks the RAM access
with large packet transfers. Just at the usage of high resolution displays with large video bandwidth require-
ment this aspect should be considered.
Now some considerations for minimum block size settings. In general the minimum values must be less or
equal to the maximum settings. These values are for controlling efficiency of IPA requests to the SDC. If
the amount of data in the FIFOs is lower the given value, no action is initiated. The IPA device waits for a
required, worthwhile packet size. The greater the packet size, the higher the throughput, but additional high-
er risk of GPU or VIC interruption due to video memory locking during longer transfer times.
2.3 Related Settings and Informations
From application point of view the setup of appropriate control information to the DIPA configuration reg-
isters is not sufficient for accessing video memory in physical address format. Additional settings are re-
quired for a complete configuration. Detailed information are in ULB and SDC documentation.
ULB handles the mapping of the video RAM address used for DPA (memory mapped). Other commands
use the In- and Output FIFOs too. Additional command processing is controlled by ULB.
SDC did the logical to physical address conversion. If picture data should be accessed, SDC calculates
based on Layer Description Record (LDR) information the physical video memory address. Layer start off-
sets and bit size of pixel data influences logical to physical address mapping. This knowledge is necessary
to locate a given picture coordinate {Layer, X, Y} at its dedicated physical memory position.
If IPA is used in DMA mode both control mechanisms for DMA buffer sizes (DMA demand mode, see ULB
description) and for IPA FIFO buffering should be considered to stay not in conflict with each other. Oth-
erwise this could lead to deadlock situations in data flow.
Page 122