MB87P2020 Datasheet, PDF (219/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

3 Register Description
CCFL Driver
3.1 Overview
Table 3-1: Control Register CCFL1
Name
Description
CCFL1_SSEL^a
Sync select 1
CCFL1_EN
CCFL enable
CCFL1_PROT
Protect settings
CCFL1_SNCS
Sync select 0
CCFL1_SYNC
Sync software trigger
-
reserved
CCFL1_SCL
Prescaler Register
a. MB87P2020-A only
Position
[28]
[27]
[26]
[25]
[24]
[23:8]
[7:0]
Reset Value
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
Name
CCFL2_FLS
CCFL2_PSE
CCFL2_IGNT
Table 3-2: Duration Register CCFL2
Description
Flash duration
Pause duration
Ionisation duration (ignition)
Position
[31:16]
[15:8]
[7:0]
Reset Value
0
0
0
Access
R/W
R/W
R/W
3.2 Control Bits
For MB87P2020-A an additional control bit for selecting sync mixer synchronization was necessary. Note
that this new control bit (CCFL1_SSEL) takes precedence over SNCS flag.
For other devices than MB87P2020-A writing to this control bit is ignored while reading returns always ’0’.
Table 3-3: Control bit description
Bit
Name
28^{a CCFL1_SSEL}
27 CCFL1_EN
26 CCFL1_PROT
Description
SYNCSEL. If this bit is not set (0), synchronization is controlled by
SNCS. Otherwise (1) the output of GPU sync mixer 5 is used for synchro-
nization.
COCADEN. If this bit is set, the Cold Cathode Driver is enabled. Other-
wise the pins have its inactive state (FET1/2=0, IGNIT=0, OFF=1).
PROTECT. If this bit is set, write access to the duration register changes
the value of the register, but the durations of the phases are not influenced
until this bit will be cleared.
If this bit is not set, a write access changes the durations immediately.
Register Description
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