MB87P2020 Datasheet, PDF (54/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
G0LINECOL = line_col;
G0CMD = GDC_CMD_DWLINE;
return (0);
};
Figure 1-6: Draw line function as an example for command synchronisation
The function in figure 1-6 writes only the command and command dependent register settings (in this case
the line colour) to display controller, data transfer is done afterwards with help of FIFOs.
word GDC_FIFO_INP(dword *p_arr, word pcnt, byte dma_ena) {
if (dma_ena == 0) {
for (;pcnt>0;pcnt--) {
while (G0FLNOM_IFF != 0) G0FLRST_IFF = 1;
G0IFIFO = *p_arr++;
}
} else {
while ((DMACA0 & 0x80000000) != 0);
DMASA0 = (IO_LWORD)p_arr;
// source address
DMACA0 = DMACA0 | 0x80000000 | 0x0E100000 | pcnt; // DMA operation enable
G0DMAFLAG_EN = 1;
}
return (0);
};
Figure 1-7: Function to put data to display controllers input FIFO
To write data to input FIFO another API function (GDC_FIFO_INP) shown in figure 1-7 is used.
GDC_FIFO_INP takes a pointer to an array with values¹ which should be written to FIFO together with
data count. Note that data count is not limited to FIFO size, it can have any size. Before data can be written
to FIFO (register: G0IFIFO) the API function polls the full flag of input FIFO in order to avoid FIFO over-
flow. The general flow for command execution and programming is discussed in chapter 1.5.2.
Optional the transfer can be controlled by DMA (parameter dma_ena). See chapter 1.7 for more details
about DMA and its handling within an application.
Both display controllers (Lavender and Jasmine) contains one input and one output FIFO. The sizes of these
FIFOs are different in display controllers and listed in table 1-10.
Table 1-10: FIFO sizes for Lavender and Jasmine
FIFO
Input FIFO
Output FIFO
Size for Lavender
128 words
128 words
Size for Jasmine
64 words
64 words
Every FIFO has a set of flags which allow a flow control by an application. A detailed description of FIFO
flags can be found in flag description located in appendix. Beside full and empty flag also two programma-
ble limits (one lower and one upper limit) is implemented in both display controllers. These limits can be
used to perform an action within an application based on a certain FIFO load. This is often more efficient
than polling the full or empty flag for every single data word. Note that every flag can cause an interrupt
(for details see chapter 1.6) so that FIFO flags can be used for interrupt based flow control.
A general rule for input FIFO should be to check whether the free space in FIFO is large enough for the
amount of data words which have to be written.
Before reading from output FIFO the application should check whether enough data are available in output
FIFO. This can be done by polling the FIFO flags or by generating an interrupt.
As a replacement of application based flow control (polling or interrupt) DMA can be used to write data to
input FIFO or read data from output FIFO. For DMA the hardware takes care about FIFO load but an ap-
1. ’dword’ means 32 Bit unsigned.
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