MB87P2020 Datasheet, PDF (304/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
Table 1-2: Register address space for Jasmine and Lavender
Register
Bits Group
Name Address
Name
Description
Default
value
SMXFCT
SSWITCH
0:
0x3204,
1:
0x320C,
2:
0x3214,
3:
0x321C,
4:
0x3224,
5:
0x322C,
6:
0x3234,
7:
0x323C
0x3240
31:0 FT
7:0 CD
PIXCLKGT 0x3248
3
HC
2
CP
1
GON
CKLOW
0x3250
0
GT
24 OP
23:16 LLR
15:8 LLG
7:0 LLB
oo
Function table
Output value =
function_table[a]
a=S4*2⁴+S3*2³+S2*2²+S1
*2¹+S0*2⁰
Sn: Value (binary) of signal
selected with SMXSIGS_Sn
0x00000000
Output signal delay (sync
switch) register
o o M Sync switch, (0=no; 1=0.5
0x00
display clock (CLKD) cycles
delay)
Pixel clock gate register; gate
is output of SM7
o o M Clock divider (0=1:1;1=1:2)
0
o o M Clock polarity (0=true;
0
1=inverted)
o o M Clock gate enable (1=on/
0
0=off)
o o M Gate type (0=And; 1=Or)
0
Colour key lower limits
(according to physical colour
space)
Pin DIS_CKEY is activated
when all pixel channels lie
within their limits (including
limits).
oo
Key out polarity
0
(0=active high, 1=active low)
oo
Red channel
0x00
oo
Green channel
0x00
oo
Blue/monochrome channel
0x00
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