MB87P2020 Datasheet, PDF (190/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
Mnemonic
(API-Names)
DIR_PXScanDots
PHSCAN_SCLK
DIR_DualScanOffs
DUALSCOF
DIR_MTimOddStart
MTIMODD_X(0)
MTIMODD_Y(0)
DIR_MTimOddStop
MTIMODD_X(1)
MTIMODD_Y(1)
DIR_MTimEvenStart
MTIMEVEN_Y(0)
DIR_MTimEvenStop
MTIMEVEN_Y(1)
DIR_MTimingOn
MTIMON
DIR_TimingDiag
TIMDIAG_X
TIMDIAG_FIELD
TIMDIAG_Y
DIR_SPG0PosOn
SPGPSON_X(i)
SPGPSON_FIELD(i)
SPGPSON_Y(i)
DIR_SPG0MaskOn
SPGMKON_X(i)
SPGMKON_FIELD(i)
SPGMKON_Y(i)
DIR_SPG0PosOff
SPGPSOF_X(i)
SPGPSO_FIELD(i)
SPGPSO_Y(i)
DIR_SPG0MaskOff
SPGMKOF_X(i)
SPGMKOF_FIELD(i)
SPGMKOF_Y(i)
DIR_SPG1PosOn
Table 4-1: GPU Register Set (continued).
Addr
Function
3008 x Physical size in scan dots (PX*BitsPerPixel/Bit-
sPerScanclock)
[29:16] = SX
300C x Dual scan Y offset (usually PY/2)
[13:0] = offset
3010 x Master timing: odd/only field start (in scan clock
cycles, with respect to visible area)
[30:16] = x (2’s complement)
[14:0] = y (2’s complement)
3014 x Master timing: odd/only field stop (in scan clock
cycles, with respect to visible area)
[30:16] = x (2’s complement)
[14:0] = y (2’s complement)
3018 x Master timing: even field start (in scan clock
cycles, with respect to visible area)
[14:0] = y (2’s complement)
301C x Master timing: even field stop (in scan clock cycles,
with respect to visible area)
[14:0] = y (2’s complement)
3020
Master timing switch
[0] = switch (0 = off, 1 = on)
3024
Diagnostic register, contains current timing posi-
tion
Initial
Value
0
0
0
0
0
0
0
0
off
read-
only
3030
Sync pulse generator 0, “switch-on” position
[30:16] = X scan position (2’s complement)
0
[14:0] = Y scan position (2’s complement)
0
[15] = field (0=odd, 1=even field)
0
3034
Sync pulse generator 0, “switch-on” don’t care vec-
tor
0
[30:0] = mask bits (1= do not include this bit into
position matching)
3038
Sync pulse generator 0, “switch-off” position
[30:16] = X scan position (2’s complement)
0
[14:0] = Y scan position (2’s complement)
0
[15] = field (0 = odd, 1 = even field)
0
303C
Sync pulse generator 0, “switch-off” don’t care
vector
0
[30:0] = mask bits (1= do not include this bit into
position matching)
3040
Sync pulse generator 1, “switch-on” position (cf.
DIR_SPG0PosOn)
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