MB87P2020 Datasheet, PDF (30/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
The GDC device has four different clock domains, that means clocks derived from four different sources.
The largest part of the design runs at core clock which operates at the highest frequency driven by the MAS-
TERCLK output. Thus normally the APLL is used to provide a higher internal operation frequency. The
next domain is the display output interface which operates at pixel clock frequency. For most applications
it is recommended that this is the clock from OSC_IN pin, divided by two¹. So the crystal oscillator has to
be choosen to have a whole-numbered multiple of the display clock frequency. Preferred routing is the DI-
RECT clock source channel since some displays require a small clock jitter which is not able to provide by
the APLL. The other clocks for MCU interface (ULB_CLK) and video interface (VSC_CLKV) are not de-
rived by the clock routing and generating part and used directly from the appropriate input pin.
Finally the generated source clocks of the for domains go to the clock gating/distribution module. There are
gated clock buffers and inverters for each GDC module implemented. Each module has it’s own clock en-
able flag which can be programmed for modules needed by the application only. This method saves power
of not used functional blocks of GDC (refere to table 3-1).
The configuration of CU is stored in two registers, ClkConR and ClkPdR, which are connected to User Log-
ic Bus for writing and reading. The bus interface consists of an address decoder and circuitry for different
access types (word, halfword and byte access over a 16 or 32 bit bus connection).
1.2 Reset Generation
GDC works with an internally synchronized, low active reset signal. The global chip reset can be triggered
by an external asynchronous reset or internally by software reset (configuration bit in ClkPdR). The external
triggered RESETX results in resetting all GDC components including the Clock Unit, however software
reset has no influence on CU internal registers.
Lavender synchronizes its external reset (RSTX pin). Reset is delayed until 4 clock cycles of each
ULB_CLK and OSC_IN are executed. This gives stability against spikes on the RSTX line but has the dis-
advantage of delayed reset response of Lavender.
For Jasmine internal reset is active immediately after tying RESETX low plus a small spike filter delay. Due
to the synchronization of RESETX the internal reset state ends after 4 clock periods of OSC_IN and 4 clock
periods of ULB_CLK after releasing RESETX pin. Reset output RSTX_SYNC for all internal GDC register
states are synchronized with OSC_IN, however internal Clock Unit registers are synchronized with
ULB_CLK in addition. Thus a minimum recovery time of 4 clock cycles of OSC_IN plus 4 cycles of
ULB_CLK is needed before writing to Clock Unit configuration registers is possible after RESETX be-
comes inactive.
The reset generator of Jasmine has a spike filter implemented, which suppresses short low pulses, typical
smaller than 9 ns. Under best case operating conditions (-40 deg. C; 2.7V; fast) maximum suppressed spike
width is specified to 5.5ns. This is the maximum reset pulse width which did not result in resetting the GDC
device. Minimum pulse width for guaranteed reset is specified to 1 clock cycle of OSC_IN (80 ns typical).
1.3 Register Set
Table 1-1 listst the clock setup registers. ClkConR (Clock Configuration Register) is mainly for generation
of the base clocks and the routing/selection from one of the four input sources. It controls the clock dividers
and the use of the APLL. The possibility to use a second clock path, called direct clock source, gives a high
flexibility for using the APLL either for MASTERCLK or PIXELCLK generation or both. Also the pin
function of DIS_PIXCLK can be defined in this register. If DIS_PIXCLK is selected as clock source the
pin should be configured as an input.
Upper 8 bits of ClkConR are used as identification of the different GDC types. Lavender is identified with
reading back a ’0x00’, Jasmine with a ’0x01’.
Use of DIS_PIXCLK as pixel clock output and selection of DIS_PIXCLK for the clock source can result in
unintentional feedbacks and has to be avoided.
1. Preferred is an even divider value to achive 50% clock duty
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