MB87P2020 Datasheet, PDF (282/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
2.5.7 Display Interface
For display settings, supported colour formats, functional timing and configuration possibilities of display
interface see Graphic Processing Unit (GPU) description. This specification describes only the physical tim-
ing of display signals.
Pixel clock output pin (DIS_PIXCLK) has a clock invert option.Thus timings are valid for both clock edges.
Table 2-13: Pixel Clock Output Timing
Parameter
max. Pixel Clock (DIS_PIXCLK) Output
Delay (r/f)^a
min. Pixel Clock (DIS_PIXCLK) Output
Hold
a. Related to internal PIXEL_CLK
Symbol
t_ODPIXCLK
@20pF [ps]
Jas
Lav
15740 11240
@50pF [ps]
Jas
Lav
17900 13410
t_OHPIXCLK 5240 3610 6090 4460
The timing values given in table 2-14 and 2-15 are related to Display clock output pin (DIS_PIXCLK). The
values are only valid if the capacitive load is the same for clock and data pins.
Because the driving clock edge for display clock (DIS_PIXCLK) is programmable (see GPU description
for more details) all possible edge combinations have to be taken into account for timing calculation.
Table 2-14: Digital Display Interface, Output Characteristics
Parameter
Symbol
max. Display Data (DIS_D) Output Delay
Time (r/f)
t_ODDISD
min. Display Data (DIS_D) Output Hold
Time (r/f)
t_OHDISD
max. Color Key (DIS_CKEY/DIS_CK) Out- t_ODCKEY
put Delay (r/f)
min. Color Key (DIS_CKEY/DIS_CK) Out- t_OHCKEY
put Hold (r/f)
max. DIS_VSYNC Output Delay (r/f)
t_ODVSYNC
min. DIS_VSYNC Output Hold (r/f)
t_OHVSYNC
max. DIS_HSYNC Output Delay (r/f)
t_ODHSYNC
min. DIS_HSYNC Output Hold (r/f)
t_OHHSYNC
max. DIS_VREF Output Delay (r/f)
t_ODVREF
min. DIS_VREF Output Hold (r/f)
t_OHVREF
@20pF [ps]
Jas
Lav
3510 4540
@50pF [ps]
Jas
Lav
4020 4930
-690 -820 -430 -600
1960 2880 2450 3320
-800 200
-530 300
2800
-4770
2420
-5050
2560
-4920
3770
-1610
3720
-1720
3710
-1720
3220
-6930
2840
-7210
2980
-7080
4200
-3780
4140
-3890
4140
-3890
Page 282