MB87P2020 Datasheet, PDF (68/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
For DMA demand mode settings according to (4) (0x3f for Jasmine, 0x7f for Lavender) to keep the input
FIFO full all the time and according to (5) to keep output FIFO flushed all the time avoid problems with
internal packetizing. Data will be transferred immediately if possible.
IFDMA_LL = FIFOSIZE – 1
(4)
OFDMA_UL = 1
(5)
For DMA Block/Step/Burst mode other trigger levels are required due to additional restriction for MCU
block transfer sizes (see equation (2) and (3) with their description).
Also at demand mode it is possible to set up other trigger levels in order to transfer more words at once. In
this cases special care should be taken to avoid the described deadlock situations. Reserve for required data
amount (IFIFO) or space (OFIFO) for packetized procession must be guaranteed all the time.
There are two possibilities to stop DMA transfer. The first is the falling edge of DMAFLAG_EN as already
mentioned. The second possibility is to interrupt the running command by a SWReset command. Because
the DMA controlled stream is normally coupled to the currently executed command¹ interruption of this
command should also cause DMA dropout. Because of FIFO reset during SWReset already transferred
data will also be deleted.
1.7.4 DMA programming examples
In figure 1-18 an example for a MCU- and Lavender DMA initialization is given. The MCU DMA channel
’0’ is used for DMA connection.
In DMACB0 and DMACA0 MCU registers the parameters for MCU-DMAC are set; with set of Bit 31 in
DMACR DMA operation is enabled inside MCU.
;;; DMA variables
blk_dma1: equ 1 ; block size
dtc_dma1: equ 0 ; transfer count
ofhigh_dma1: equ 1 ; DMA limit
dma1a: equ 0x8e100000 + (blk_dma1 << 16) + dtc_dma1) ; build data word for DMACA0
dma1of: equ (ofhigh_dma1 << 16)
;; ---------------------------------
;; Init DMA for Data output
;; ---------------------------------
writereg DMASA0,
G0OFIFO ; source address
writereg DMADA0,
0x001c0000 ; destination address
writereg DMACB0,
0x28000004 ; type=00,md=10(demand),ws=10(word),inc.destination
writereg DMACR,
0x80000000 ; enable MCU-DMAC
writereg DMACA0,
dma1a
writereg G0OFDMA,
dma1of
writereg G0DMAFLAG, 0x00000206 ; OF, EN_DMA=1, demand mode, DSTP=2
; writereg G0DMAFLAG, 0x0000021E ; OF, EN_DMA=1, demand mode, DSTP=2, INV, TRI
; wait for DMA to finish
waitdma2:
readreg DMACA0 ;nach r2
ldi
#0x80000000, r3
and
r3, r2
bne
waitdma2
Figure 1-18: MCU- and GDC-DMA initialization example
1. For input FIFO it is also possible to deliver data for waiting command (see section 1.5). But the SWReset
command flushes the command pipeline completely so that also the waiting command will be deleted. DMA
transfer has to stop anyway.
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