MB87P2020 Datasheet, PDF (38/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
An example sequence for this procedure is listed below:
/* CU control information */
G0CLKPDR = 0x00008800; // SW reset and APLL enable
G0CLKPDR = 0x00000800; // release SW reset, clock gates are still closed
G0CLKCR = 0x010E8001; // MASTER=XTAL*15/2, PIXCLK=XTAL/2 not inverted output
G0CLKPDR = 0x00000EF1; // enable GPU, ULB, CCFL, SDC, VIC, DIPA, PE
Figure 3-3: Clock configuration procedure with reset
3.3 Application Notes
The Clock Unit provides an internally synchronized reset signal to all GDC components. Therefore it’s nec-
essary to have a stable clock applied to the OSC_IN pin during RESETX is low and/or at least after release
of RESETX. Otherwise the internal circuitry is not initialized properly or clock unstability after reset release
can cause malfunction.
With the direct clock source it’s possible to use a external ULB_CLK from the MCU or RCLK as clock
source for almost all internal GDC components. The APLL is not able to handle jitter/variations in input
clock.
If the GDC should operate in single clock mode over ULB_CLK driven by the MCU, ULB_CLK and
OSC_IN have to be bridged. In any case a clock has to feed in OSC_IN pin, otherwise the reset state would
not be left.
If system or pixel clock divider are initialized with an even value tis results in an odd divider value (value
interpreted +1). In this situation the duty of the output clock is not even 1:1. Most important this is for low
values. In case of not even duty the high duration is smaller than the low duration. Following table lists clock
divider and duty relationship.
Setup Value
0
1
2
3
4
5
6
...
Table 3-2: Clock division and resulting duty
Divider
1
1/1
2
1/1
3
2/1
4
1/1
5
3/2
6
1/1
7
4/3
Duty
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