MB87P2020 Datasheet, PDF (176/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
There is a special case: TV-conform timing requires that every other frame consists of an odd number of
lines to achieve an odd sum of lines for two consecutive frames (representing the two fields of an interlaced
TV picture). Therefore, an additional coordinate had to be introduced, referred to as field bit, thus actually
expanding the coordinate space to three dimensions. Even for this case the number of visible pixels remain
constant, what differs is the number of blanking lines.
These “timing coordinates” form the basis for all timing-related signal generation. For a complete descrip-
tion a maximum six timing and three geometrical parameters are necessary. The geometrical parameters are
the number of scan dots in each direction, i.e. the area with visible pixels on the physical display, and the
extra DualScanOffs parameter for dual scan displays (i.e. the number of lines of each display segment).
The number of necessary timing parameters is either four or six, depending whether or not field toggling is
enabled (i.e. frames with differing number of blanking lines are used). For normal operation a set of four
timing parameters is sufficient: xstart, xstop, ystart, and ystop. The “timing coordinates” men-
tioned above cover a range from [xstart, ystart] to and including [xstop, ystop]. If field toggling
is used, then there is a pair of (ystart, ystop) values for every frame type, which is used alternatively.
This explanation applies also to dual scan displays with the distinction that the Y values describe only the
upper display segment, the lower segment simply is assigned the same timing (since its respective pixel
stream is output in parallel to the upper segment).
3.10 Generation of Sync Signals
3.10.1 Overview
To achieve maximal flexibility, generation of sync signals is a three stage approach. In a first stage, signals
are generated which carry positional timing information (according to the timing coordinates described in
the section before). There are two methods to obtain these signals. The second stage combines them to form
more complex waveforms. The third stage is used for a programmable delay of half a pixel clock cycle.
During display operation the sync generating components are provided with the current timing position as
integer numbers in 2’s complement representation.
3.10.2 Position Matching
One way to form first-stage signals is a simple position matching to trigger an RS-flip-flop. This is done by
an array of six identical sync pulse generators (SPGs). Fig. 3-8 shows the working principle.
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