MB87P2020 Datasheet, PDF (285/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

AC Characteristics
other SDRAM interface pins timing is not guaranteed to follow this specification. Thus all connections to
the SDRAM should have same wire length.
Table 2-20: SDRAM Clock Output Timing
Parameter
max. SDRAM Clock (SDC_CLK) Output
Delay Time
min. SDRAM Clock (SDC_CLK) Output
Hold Time
Symbol
t_ODSDCCLK
t_OHSDCCLK
@10pF [ps]
7100
@30pF [ps]
8470
2850
3480
Due to configurable SDRAM interface timing, setup value of SDIF register should be considered. The con-
figuration register has two bits for each signal group:
• SDIF_TAO for address, control (ras/cas/we), CKE and DQM output delays
• SDIF_TDO for data output delay
• SDIF_TDI for data input sampling delay and
• SDIF_TOE for controlling tri-state enable of the data output buffers.
Table 2-21 specifies the possible delay shifts, commonly valid for address, command, CKE, DQM and data
ports.
Table 2-21: Configurable Delay Shifts by SDIF
SDIF Setup
Min Delay Shift [ps]
Max Delay Shift [ps]
00_b
0
0
01_b
650
1920
10_b
1240
3620
11_b
1720
5030
SDRAM port timing specifications in table 2-22 are valid for a configured delay value 00_b.
The user can add the given delay shifts to the appropriate minimum and maximum values for different con-
figurations.
Note that additional delay shifts have to be subtracted for input setup timings and delay shifts have to be
added for output delay, output hold and input hold timings.
For data input this could be used to shift the data sampling point later with regard to the internal clock.
For calculating shifted output parameters the user should take minimum delay shifts for MIN delay/hold
and maximum delay shifts for MAX delay/hold. However input characteristics are always valid under MAX
operating conditions and have to be shifted by delay shift value given in MAX column. Input characteristics
are given in the MIN column because they are minimum requirements.
The timing values given in table 2-22 and table 2-23 are related to Lavender SDRAM clock pin
(SDC_CLK).
Because the clock output path depends on external capacitance also the input setup and hold times are ca-
pacitance dependend which is normally not the case (see also chapter 2.5.2).
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