MB87P2020 Datasheet, PDF (345/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Hints and Restrictions
Table 2-8: Overview for direct SDRAM access with 16bit and 8bit data mode
Subject
Solution/Workaround
Concerned devices
Testcase
Description
Always read 32bit (word) values from Lavender SDRAM space and mask
the data afterwards if necessary.
For Jasmine this problem is solved.
MB87J2120 (Lavender)
fixed for MB87P2020 (Jasmine)
fixed for MB87P2020-A (Jasmine redesign)
EMDC: SDC.3 and DPA.1
2.7 Input FIFO read in 16bit mode
One hidden feature of Lavender and Jasmine is the reading from input FIFO¹. Normally reading from input
FIFO makes no sense and is therefore not officially supported but it may be the reason for a MCU blocking
which can occur when reading from this address is performed by accident.
In 16bit data mode (Pin MODE[2]=0) reading from input FIFO can cause the ULB_RDY pin to stay in ac-
tive state (logic ’0’). As already described in chapter 1.6 this can block the command execution of MCU.
To avoid this problem reading from input FIFO should not be used in 16bit data mode.
This problem occurs on both GDC devices but for Jasmine the ULB_RDY timeout can be set so that no
system blocking can occur.
Table 2-9 gives an overview and a classification about the described problem.
Table 2-9: Overview for input FIFO read access in 16bit data mode
Subject
Description
Classification
Effects without
workaround
Solution/Workaround
Concerned devices
Testcase
Description
Reading from input FIFO in 16bit data mode causes ULB_RDY = 0.
HW limitation
The hanging ULB_RDY signal blocks the command execution of a
MB91360 series MCU.
Do not read from input FIFO (address 0x0004) in 16bit data mode.
For Jasmine the ULB_RDY timeout can be activated.
MB87J2120 (Lavender)
MB87P2020 (Jasmine)
MB87P2020-A (Jasmine redesign)
EMDC: CTRL.1 (I/O march)
2.8 ULB_DSTP pin function
ULB_DSTP output of Lavender/Jasmine must not be used because it can not be guaranteed that ULB_DSTP
signal is always generated at DMA interruption by SW-Reset or falling edge of DMAFLAG_EN². It is rec-
1. The read value is the current FIFO output value which will be delivered to Pixel Processor (PP) with next
FIFO read access. Note that the PP reads with core clock data from input FIFO while MCU reading can only
be performed with ULB clock. Because ULB clock is always slower (or at most equal) than core clock not all
FIFO output data can be sampled.
2. See ULB specification in hardware manual for further details.
Restrictions
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