MB87P2020 Datasheet, PDF (140/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
R
G
B
RGB888
V
Y
U
YUV444
R
G
B
RGB555
R
G
B
RGB565
V
Y
U
YUV555
V
Y
U
YUV655
V
Y
U
YUV422
Figure 3-2: Possible Color occupancy in register VICALPHA
VICCTRL (4008H):
The VICCTRL register contains settings for color mode, clock mode, port mode and byte swap. Those set-
tings should be done according to settings of external video decoder. Please use only suggestive combina-
tions of color-, clock- and port-mode.
VICFCTRL (400CH):
bit [3:0] (FST), [7:4] (SEC), [11:8] (TRD):
GDC’s memory space is divided in up to 16 areas (layer). Each of them has a logical layer address and can
contain video data. VIC implies a frame synchronization controller which mangages two or three layers
needed for frame synchronization (see register VICFSYNC). Layer addresses for VIC could be defined in
register VICFCTRL. Note that same addresses are allowed, but field/frame synchronization won't work cor-
rectly.
Related registers: VICSTART, VICFSYNC
bit 16 and 17 (EVENEN and ODDEN):
If those flags are set to zero, every field of the specified type (odd/even) will be skipped. So EVENEN (en-
able even fields) and ODDEN (enable odd fields) submit selection of field type. It is recommended to enable
only one field type to supress field jumping during displaying video layers. Function is to be seen in context
with VICFCTRL[20] (SKIP). Those flags have no relevance if VICFCTRL[21] (FRAME) is set.
Related registers: VICFCTRL[18], VICFCTRL[22:20]
bit 18 (VICEN):
The VICEN (VIC enable) switches video interface unit on (1) or off (0), („main switch“). It does also enable
or disable synchronization of video in- and output.
Related registers: VICFCTRL[17:16], VICFCTRL[22:20]
bit 20 (SKIP):
This flag controls the skip function of VIC. If SKIP is set to 1, every second field of each field type is
skipped. Skip enable function is to be seen in closed connection with VICFCTRL[16] (EVENEN) and
VICFCTRL[17] (ODDEN). If both of them and SKIP are set to one, every second frame is skipped. So it is
possible to reduce data rate between VIC and SDRAM to a half of the output data rate from external video
pixel decoder. A quarter of input data rate can be achieved be enabling only one field and skip. An example
is shown in the following figure (figure 3-3).
Related registers: VICFCTRL[18:16], VICFCTRL[22:21]
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