MB87P2020 Datasheet, PDF (93/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

SDRAM Controller
• Sampling time for SDRAM data outputs (tDCBTdin)
• Delay for switching the tri state buffer enable signal (tDCBToe)
Figure 2-2 shows the schematic of the implemented SDRAM interface circuitry. Variable clock line delays
ras, cas, we, dqm, cke
DQ
addr
DQ
addr_delay
oe
DQ
RAS
CAS
WE
DQM
A
tristate_delay
wdata_sdram
DQ
dout_delay
rdata_sdram
QD
CLKK
din_delay
configurable interface
clock delay registers
signal and
clock driver
DQ
CLK
external
wire delay
Figure 2-2: Design of SDRAM Interface
are implemented as buffer chains with multiplexed taps. The multiplexers respective the resulting delays
are controlled by a two-bit value for each signal group in the delay configuration byte. Under typical con-
ditions a programmable range from nearly 1ns up to 4ns is possible in steps of 1ns.
Recommended values for the interface setup are tDCBTaout=2ns, tDCBTdout=2ns, tDCBTdin=3ns and
tDCBToe=1ns.
2.2 Integrated SDRAM Implementation (Jasmine)
Jasmine has no interface to external SDRAM. Delay adjustment is not needed and not implemented for the
integrated solution.
SDRAM Ports
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