MB87P2020 Datasheet, PDF (130/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
Table 2-1: Supported Video color formats for Lavender and Jasmine
Format
RGB555
YUV555
YUV655
Lavender
yes
-
-
Jasmine
yes
yes
yes
Comment
Lavender does not contain a YUV to
RGB conversation (see GPU
description)
Lavender does not contain a YUV to
RGB conversation (see GPU
description)
2.3 Data Input Timing
The VIC component supports three different input timing modes which can be selected using register
VICVISYN_SEL. The preferred and default mode is denoted "Videoscaler-Mode" in the following.
2.3.1 Videoscaler-Mode
Videoscaler-Mode has been implemented for VPX Video Pixel Decoder family (Micronas Intermetall),
which provides up to 16 data bits (DATA; Pin: VSC_D[15:0]), a video clock (CLKV; Pin: VSC_CLKV),
a vertical synchronization signal (VREF; Pin: VSC_VREF), a field identification signal (FIELD;
Pin: VSC_IDENT), a horizontal video active signal (VACT; Pin: VSC_VACT) and additional an optional
alpha key signal (ALPHA; Pin: VSC_ALPHA). Other video deocoders are supported if they provide a sim-
ilar interface and timing. See timing diagram (figure 2-3) for detailed information.
VREF
FIELD
VACT
DATA
2..9 lines
>1 clock cycle
1 line
Figure 2-3: Videoscaler timing (general)
VREF pulse indicates the start of a new field. FIELD changes should happen at least one clock cycle before
negative edge of VREF (see figure 2-3).
VACT marks an active video line. Due to downscale function of Videoscaler inactive lines are possible.
Positive edge of VACT indicates the start of an active line, negative edge denotes the end of line. During
VACT is active, VIC samples data received on data ports and writes them into Video Memory (SDRAM).
Polarities of control signals are adjustable, see register VICPCTRL.
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