MB87P2020 Datasheet, PDF (83/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

SDRAM Controller
1.5.1 Elucidations regarding Address Mapping
1.5.1.1 Block Structure of Pixel Data
DRAMs have not equal access timings if randomly accessed. If a ROW address is already activated, faster
access can be done. Each ROW consists of 256 COL addresses.
As compromise between horizontal and vertical operation a block oriented access scheme is implemented.
A block is identical with one ROW, each 256 COL addresses with faster access. Disadvantage of this block
structure is a more complicated pixel addressing over direct physical access methods. Block size is defined
to 8 words horizontal¹ and 32 lines vertical². For example, this results to 32x32 pixel block size at 8 bpp.
If bank interleaving is used (on Lavender chip), same ROW address for each of the 4 banks are combined
to a macro block with double size in horizontal and vertical dimension. This gives the chance to activate a
ROW in another bank before reading from it during access is running on another bank. This hides row ac-
cess time in most cases.
For access by pixel address the block structure is not relevant. It is mapped automatically by hardware to
the right physical address. If non-picture data or data which should not be displayed is stored via physical
access, address can be interpreted as linear space without rows, banks and columns. Only if physical access
on graphic data is required, the block based philosophy should be considered.
1.number of pixels depending on color depth (bpp)
2.word and pixel have same meaning
Function Description
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