MB87P2020 Datasheet, PDF (116/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
bus connected to the AAF. AAF requires at minimum two extra clock cycles which is needed for internal
data processing.
1.
2.
3.
CLKK
RVALID
RDATA(31:0)
WVALID
WDATA(31:0)
2 clock cycles
3 clock cycles
set by tRW register
(minimum 10/7)
Figure 1-3: Timing for read-modify-write on SDC bus for AAF access
Description of events at clock cycles from figure 1-3:
1. At this edge the AAF takes the pixel data of the old pixel from RDATA bus (SDC side).
2. At this event the AAF sets the result at the WDATA bus.
3. SDC takes the pixel data of new pixel from the WDATA bus.
Note!
The delay between RVALID (1.) and WVALID (2.) can be bigger, but not smaller!
To gain more system performance, tRW is possible to reduce to 8 (Lavender) or 5(Jasmine) if Antialiasing
Filter is bypassed. No other module has any requirements to this read-write timing. The minimum values of
8/5 guarantee that there will be no bus conflict at the SDRAM interface itself. The setting of tRW is inde-
pendent from core clock frequency.
Table 1-5: Minimum settings for tRW
AAF on
AAF off
Jasmine
7
5
Lavender
10
8
There is no requiremnt to reduce tRW setting to its minimum. It is only an aspect of performance tuniung.
Additional it did not that much influence system performance, it is save to setup a value of 10 or 7 all the
time.
Page 116