MB87P2020 Datasheet, PDF (319/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

2 Flag Description
Flag Description
Table 2-1 contains all flags for MB87P2020-A (Jasmine) and MB87J2120 (Lavender).
In order to avoid data inconsistencies during bit masking within flag register a mask (and/or gating) process
is implemented in hardware for flag register. To distinguish between flag set-, reset- and direct write access
different addresses are used¹:
• FLNOM (0x000C):normal write operation
• FLRST (0x0010):reset operation (1: reset flag on specified position; 0: don’t touch)
• FLSET (0x0014):set operation (1: set flag on specified position; 0: don’t touch)
All of these three addresses write physically to one register with three different methods.
For reading all three addresses return the value of flag register.
Every flag can have a different reset behaviour. With help of register FLAGRES the application can choose
whether the hardware is allowed to reset the desired flag (dynamic behaviour, FLAGRES_x=1) or not (stat-
ic behaviour, FLAGRES_x=0). With dynamic behaviour the flag follows the driving hardware signal while
with static behaviour the application is responsible for resetting the flag in order to catch next event. In
table 2-1 the default reset behaviour at system start up is given in last column.
Note that some flags are only available for Jasmine..
Table 2-1: Flags for MB87J2120 (Lavender) and MB87P2020-A (Jasmine)
Name Bit
Description
Default
behaviour
(FLAGRES)
VICSYN
ERDY
RDPA
FDPA
RIPA
RMCP
A frame or field has been written to or read from
SDRAM
Which event is signalled by this flag depends on VIC set-
tings:
31
X VICFCTRL_FRAME determines the storage type within
SDRAM (field or frame). For details see VIC description
and register list.
VICVISYN_START determines whether a write or read
start should trigger the flag
RDY timeout error has occurred
30
X See ULB description and register description for RDYTO
and RDYADDR
1: DPA write access is enabled.
This flag has to be polled before each DPA (write-)
29 X X _{access to ensure a save SDRAM accessa. Otherwise data}
loss may occur.
28
X
X
1: DPA has finished SDRAM access and is ready for next
one.
27 X X ^{1: IPA is ready for command execution}
26 X X ^{1: MCP is ready for command execution}
static
(0)
static
(0)
dynamic
(1)
static
(0)
static
(0)
static
(0)
1. Additionally all access types (word, halfword and byte) are possible for each of these addresses.
Flag Description
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