MB87P2020 Datasheet, PDF (309/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Register Description
Table 1-2: Register address space for Jasmine and Lavender
Register
Bits Group
Name Address
Name
Description
Default
value
VICFSYNC 0x4014
16 REL
15 SYNC
14:0 SWL
VICCSYNC 0x4018
1:0 MODE
SDRAM
0x401C
VICBSTA
0x4020
2:0 LP
6:4 HP
VICRLAY
0x4024
19:16 AOVL
11:8 LIVL
3:0 AIVL
Control register for video I/O
synchronization
oo
1: VIC is faster than GPU
0: GPU is faster than VIC
oo
1: Three layer mode
0: Two layer mode
oo
Switch level for layer switch
in two layer sync mode
Control Word for clock syn-
chronization (Lavender only)
o
Sync Mode
00: Core Clock > Video
Clock
01: Core Clock > 2*Video
Clock
10: Core Clock = Video
Clock
11: Reserved
SDRAM request priority con-
trol register
oo
Low priority
oo
High priority
o o R VIC status register for test
purpose (read only)
Video layer debug register for
test purpose (read only)
o R Current output layer (to GPU)
o R Last input layer (VIC)
o R Current input layer (VIC)
0
0
0
00
0x2
0x6
undef
undef
undef
Register Description
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