MB87P2020 Datasheet, PDF (143/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Video Interface Controller
every new input frame. The next GPU layer is synchronized depending on current VIC layer and vertical
position of write pointer (in this layer) which will be compared with SWL. If current vertical write position
is above the programmable threshold SWL, the current VIC write layer will be allocated to GPU because an
overtaking of read and write pointer in the same layer is excluded. Otherwise (SWL is less than VIC write
pointer) the frame synchronization unit denotes the inactive VIC layer to be the next active GPU layer.
Releated registers: VICFSYNC[15], VICSYNC[14:0], VICFCTRL[3:0], VICFCTRL[7:4]
input frames (interleaced)
0_even 0_odd 1_even 1_odd 2_{even 2odd} 3_even 3_odd 4_{even 4odd} 5_{even 5odd}
A
B
output frames (progressive)
0
0
0
A
A
A
A
B
input layer
1
1
2
B
B
A
output layer
A
B
3
3
4
B
B
A
time
5
B time
Figure 3-6: Example of frame synchronization: video output is faster than video input
bits [14:0] (SWL):
This bit has only effect if VICFSYNC[15] is set to 0 (2-layer-mode).
For explanation of SWL in context with VICFSYNC[16] (REL) see previous point. SWL will be compared
with the vertical address. Note that this address (and SWL too) includes an offset (VICSTART[13:0]). If
frame mode is enabled (VICFCTRL[21] = 1), SWL indicates the field (0: even, 1: odd) where SWL is located.
In field mode (VICFCTRL[21] = 0) SWL[14] has no function (should be set to 0).
Releated registers: VICFSYNC[16], VICSYNC[15], VICFCTRL[3:0], VICFCTRL[7:4]
VICRLAY (4024H):
VICRLAY contains some layer information, which can be read from ULB (i.e. after a picture start was in-
dicated). Three different informations will be given:
• VICRLAY[3:0] (AIVL) - this is the layer video data will be written in currently
• VICRLAY[11:8] (LIVL) - this is the previous written video layer
• VICRLAY[23:16] (AOVL) - this is the current displayed video layer
VICRLAY is a read only register.
Related registers: VICVISYN[8], VICFCTRL[11:8], VICFCTRL[7:4], VICFCTRL[3:0]
VICVISYN (4028H):
bit [1:0] (SEL):
Switches to select an input timing scheme. In Videoscaler-Mode (b'00) VIC interface uses explicit synchro-
nization signals. Polarity of those signals can be selected by VICPCTRL. SEL=0b10 is a similar timing
scheme as Videoscaler-Mode, polarity can be controlled by EXTPCTRL. CCIR-mode uses timing reference
codes merged into the data stream. No explicit control signals are used.
bit[8] (START):
Both, VIC and GPU, generate their own picture start signal. It indicates the begin of writing (VIC) or read-
ing (GPU) a new picture into or from data RAM. One flag (FLNOM_VICSYN) indicates the picture start to
VIC settings
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