MB87P2020 Datasheet, PDF (295/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Register Description
Table 1-2: Register address space for Jasmine and Lavender
Register
Bits Group
Name Address
Name
Description
Default
value
DMAFLAG
FLAGRES
ULBDEB
0x0090
12:8 DSTP
4
TRI
3
INV
2
MODE
1
EN
0
IO
0x0094
31:0 -
0x0098
23:16 IFLC
22:16
15:8 OF
14:8
7:0 IF
6:0
DMA flag register
oo
Duration of DSTP signal.
This value can be set in order
to ensure a save MCU-
DMAC reset. Normally the
default value should work.
o
1: Open drain for
ULB_DREQ, ULB_DSTP,
ULB_INTRQ
o
1: Invert ULB_DREQ,
ULB_DSTP, ULB_INTRQ
oo
’1’: DMA demand mode
’0’: DMA block/step- or burst
mode
oo
’1’: enable DMA
oo
’1’: use DMA for input FIFO
’0’: use DMA for output
FIFO
Flag behaviour register^a
oo
1: set flag to dynamic behav-
iour^b
0: set flag to static behaviour
FIFO debug register (read
only)
o
R Input FIFO load for current
command
o
Attention: This value
changes with core clock; cor-
rect sampling by MCU can’t
be ensured.
o
R Output FIFO load
Attention: This value
o
changes with core clock; cor-
rect sampling by MCU can’t
be ensured.
o
R Input FIFO load independent
from current command
o
Attention: This value
changes with core clock; cor-
rect sampling by MCU can’t
be ensured.
7
0
0
0
0
1
0x20400000
0x00
0x00
0x00
Register Description
Page 295