MB87P2020 Datasheet, PDF (94/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
3 Configuration
3.1 Register Summary
A summary of Initialization control registers is given in Table 3-1. Defaults are for 100 MHz operation fre-
quency. Address definitions for symbolic word addresses are in the file ’cbp_const.v’.
Table 3-1: Configuration Information of SDC
Symbol
SDWAIT_OPT
SDWAIT_TRP
SDWAIT_TRRD
SDWAIT_TRAS
SDWAIT_TRCD
SDWAIT_TRW
SDINIT
SDRFSH
SDSEQRAM[]
[0:63] Lavender
[0:31] Jasmine
SDMODE
SDIF_TAO
SDIF_TDO
SDIF_TDI
SDIF_TOE
Bits
Description
Reset Value
[20]
Interleave Opt^a: Execute Precharge and Acti- ¹
vate during running Bursts of previous access. ^{unused Jasmine}
[19:16] tRP: RAS Precharge Time (PRE -> ACTV,
2
default 2 wait states)
[15:12] _tRRD^b_{: RAS to RAS Bank Active Delay Time} 1
(ACTV -> ACTV, default 1 wait state)
unused Jasmine
[11:8] tRAS: RAS Active Time (ACTV -> PRE,
5
default 5 wait states)
[7:4] tRCD: RAS to CAS Delay Time (ACTV -> 2
READ|WRIT, default 2 wait states)
[3:0] tRW: Read to Write Recovery Time (READ -> 3 !
WRIT, default 7 wait states)
Wrong reset value, Jasmine requires 7/5, Lav-
ender 10/8, depending on used AAF or not.
[15:0] Init Period: Power On Stabilization Time
(default 20000)
20000
[15:0] Refresh Period: Single Row Refresh Period
(default 1600)
1600
[13:0]
Sequencer RAM [13:0], 64 words
[13:7]addr, [6:4]instr, [3:0]{ras,cas,we,ap}
(Jasmine has [12:7] address argument)
undefined
[12:0]
MRS^c: SDRAM Mode Register
[9] burst write enable, [6:4] CL, [3] interleave
burst, [2:0] burst length (0:3)=1,2,4,8 / 7=full
(default 0x033)
0x0033
Lavender only
[7:6] _tDCBTaout^d_{: Address output register clock}
0
delay (controls also CKE, DQM, RAS, CAS, ^{Lavender only}
WE outputs)
[5:4] tDCBTdout: Data output register clock delay 0
Lavender only
[3:2] tDCBTdin: Data input register clock delay
0
Lavender only
[1:0] tDCBToe: Output enable register clock delay 0
Lavender only
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