MB87P2020 Datasheet, PDF (51/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

User Logic Bus
access. In difference to a register which can be exclusively accessed via its address in MCU address space
the SDRAM is a resource that has to be shared between different display controller components. For one
special SDRAM address many different ways to access it¹ can be found. Therefore the SDRAM controller
(SDC) arbitrates the accesses with different priority.
For the direct SDRAM access does this mean that an undefined access time depending on current system
load occurs. For read accesses the ULB_RDY signal is used for synchronisation between MCU and display
controller while for write accesses a flag (RDPA) in flag register is used. The application has to poll this flag
(wait as long as flag is zero²) in order to synchronize write accesses to SDRAM window. As a side effect
no DMA access is possible for writing to SDRAM window. Since for reading the ULB_RDY signal is used
DMA access is possible.
While for Jasmine every kind of access (word (32 Bit), halfword (16 Bit) and byte (8 Bit)) is possible for
reading and writing to/from SDRAM windows for Lavender the read access is limited to word access
(32 Bit).
Table 1-7 sums up the access types and synchronization methods for both display controllers.
Table 1-7: Access type and synchronisation for Lavender and Jasmine
Access
Read
Write
Item
Synchronisation
Access
DMA
Synchronisation
Access
DMA
Lavender
ULB_RDY signal
word
possible
Flag: FLNOM_RDPA
word, halfword, byte
-
Jasmine
ULB_RDY signal
word, halfword, byte
possible
Flag: FLNOM_RDPA
word, halfword, byte
-
Because of the SDRAM access arbitration and write restrictions (flag polling) direct physical SDRAM ac-
cess is not the best method to access SDRAM memory.
For logical pixel access it is recommended to use command based and FIFO buffered drawing and access
functions (see chapter 1.5).
A better way to access the SDRAM memory in physical addressing mode is the indirect SDRAM memory
access via IPA component of display controller. This access type has some advantages compared to direct
access:
• linear access to SDRAM without window limits
• FIFO buffered transfer for effective SDRAM access
• address auto increment for reading and writing (burst SDRAM access)
• DMA is possible for reading and writing
1.4.4 Display controller bus access types (word, halfword, byte)
The MB91xxxx MCUs support three different bus access types for writing data from MCU to display con-
troller.
• Word access: write 32Bit
• Halfword access: write 16Bit
• Byte access: write 8Bit
For a more detailed description see MB91360 series hardware manual.
1. Beside the described direct physical access the Pixel Processor can access with logical addresses and also an
indirect physical access (command based) via IPA is possible.
2. Make sure this flag is set to dynamic behaviour.
Functional description
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