MB87P2020 Datasheet, PDF (79/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

SDRAM Controller
Table 1-2: SDRAM Command Timings
Parameter
Default Jasmine
Description
tRCD (RAS to CAS Delay 30 ns
Time)
22.5 ns
Time from same row ACTV to READ or WRIT
command
tRW (Read to Write
Recovery Time)^a
10 (8) T 7 (5) T
Pipeline recovery time from each READ to
WRIT command
a.This setup is not regarding DRAM timing, but required to avoid bus collision on internal busses
or external SDRAM tri-state busses due to pipelined operation. Values in parenthesis are possible
if anti aliasing filter is switched off and then no read-modify-write access is required.
clocks of idling before the next SDRAM access command. So the configuration value is lower by one than
the required timing from the SDRAM data sheet. If an absolute minimum time is given it’s necessary to
evaluate the corresponding number of clock periods for configuration. This depends on and should be op-
timized for the required core clock frequency.
Following procedure should be used:
1. divide given timing by the core clock period
2. round up to next integer
3. subtract one to have the right wait-state value
CAS Latency can be setup to values of 2 or 3 for Lavender. Jasmine is not programmable for different CL
values.
Additional configurable options are the refresh period (normally 16 us for one row) and the power on sta-
bilization timer (200 us) before the first initialization sequence begins to run. The refresh counter is reset
after each execution of a single row refresh job (not considering if it runs as time-out or idle task) and it
causes an time-out if the counter value reaches zero. The configuration values are given in a number of sys-
tem clocks.
1.4 Sequencer for Refresh and Power Down
Fixed command sequences such as SDRAM initialization, auto refresh, power down or wake-up and trans-
fers of special data structures are easier to implement in a fixed and preprogrammed manner. These tasks
are assigned to the sequencer unit of SDC.
To keep the amount of memory low and guarantee a defined device shutdown the power down sequences
are not a part inside the standard micro program for refresh and initialization. However special power down
sequences are loaded into memory when needed. If the SDC currently processes a transfer controlled by the
address/command generator unit these sequence will be finished normally and then the new loaded routine
inside the micro program storage is executed.
One word of micro program code consists of an address argument (bits [12:6] for Lavender, bits [11:6] for
Jasmine¹), flow control instruction and a container command (SDRAM command).² Figure 1-2 shows the
not used
31
Figure 1-2: Micro program entry
address
instr sdram_cmd
13 12
65
43
10
format of one micro program entry. Bits [3:1] of SDRAM command coding the RAS, CAS and WE signal.
The internal representation is inverted compared with the SDRAM ports. Bit [0] for controlling the auto
precharge (AP) feature is not controllable by the sequencer and internally fixed to ’0’. Table 1-3 lists the
1.Jasmine has reduces sequencer size of 32 words. Thus address argument is 5 bit only.
2.Logical address operations and data validation flag are not needed in this application without
preprogrammed data structures.
Function Description
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