MB87P2020 Datasheet, PDF (36/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
3 Clock Setup and Configuration
3.1 Configurable Circuitry
Clock configuration can be easily done by setting up both registers ClkConR (Clock Configuration Regis-
ter) and ClkPdR (Clock Power Down Register). ClkConR mainly controls the setup of multiplexers and
clock dividers in the main part of CU, which is shown in figure 3-1.
[23:22] {11}
[15]
OSC_IN
DIS_PIXCLK
ULB_CLK
RCLK
[31:30]
Default Path
ClkConR [ bits ]
ClkPdR { bits }
lock {12}
S
L
A _APLL X PLL CLOCK
CK
FB
[14]
[21:16]
DIV y
DIRECT
[29:24]
DIV z
[13]
[10:0]
DIV x
Figure 3-1: Clock routing and configuration bits
tst
MASTERCLK
tst
PIXELCLK
XZ_CU_PIXCK
[12]
(tristate)
ClkPdR decides which clocks should be enabled and distributed to the appropriate modules, listed in table
2-1. During change of ClkConR all enable bits in ClkPdR[10:0] have to be turned off to attain spike protec-
tion.
Table 3-1: Mapping of clock sources, outputs and their enable bits
ClkPdR Control Bit
0|1|2|3
0
1
2
3
4
5
5
6
7
8
9
Clock Source
Master^a
Master
Master
Master
Master
Master
Master
Video Scaler (VSC_CLKV)
Master
Master
MCU Bus (ULB_CLK)
Master
9
MCU Bus (ULB_CLK)
Clock Output
Pixel Processor (PP)
PP: Pixel Engine
PP: Memory Access Unit
PP: Memory Copy
Anti Aliasing Filter
Direct/Indirect Physical Access
Video Interface
Video Interface
SDRAM Controller
Cold Cathode Fluorescence Light
Serial Peripheral Bus
User Logic Bus Interface and Com-
mand Controller
User Logic Bus Interface
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