MB87P2020 Datasheet, PDF (66/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
Figure 1-16: Write DMA in block mode
1.7.3 DMA settings
In order to use DMA feature for display controller it is necessary to set up DMA according to table 1-13.
DMAFLAG_EN is the general DMA enable flag; if this bit is set to ’0’ all DMA operations are stopped. Ad-
ditionally the falling edge of this flag during a running DMA transfer causes a reset of GDC-DMAC and
MCU-DMAC via ULB_DSTP signal in order to stop DMA transfer completely. This is important because
the transferred data belong to a command and a running DMA transfer influences next command and its
data stream which is not necessarily controlled by DMA.
Table 1-13: DMA register settings
Register
Name
Address
IFDMA
0x0088
Bits
7/6^a:0
Flag
name
LL
OFDMA
0x008C _23/22^a_:16 UL
12:8
DSTP
DMAFLAG 0x0090
2
MODE
1
EN
0
IO
a. Lavender/Jasmine value due to different FIFO sizes
Description
• Lower limit for DMA access to
input FIFO
• Upper limit for DMA access
from output FIFO
• Duration of ULB_DSTP signal in
ULB clocks.
• ’1’: DMA demand mode
• ’0’: DMA block/step- or burst
mode
• ’1’: enable DMA
• ’1’: use DMA for input FIFO
• ’0’: use DMA for output FIFO
Default
value
10
60
7
0
0
1
For DMA operation only one DMA channel is available between display controller and MCU. Therefore
only one FIFO can be written or read per DMA at a given time. The programmer can select the FIFO that
should be read or written with help of DMA by set DMAFLAG_IO according to table 1-13. An additional
gate with ULB_WRX or ULB_RDX ensures that only accesses for the selected mode are accepted.
The selected DMA mode can be selected with DMAFLAG_MODE. See chapter 1.7.2 for more details
about DMA modes.
The trigger condition for DMA start can be set separately for input (IFDMA_LL) and output FIFO
(OFDMA_UL). It represents a FIFO load and is completely independent from flag settings according to flag
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