MB87P2020 Datasheet, PDF (132/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
F-bit:
• '0' during field number 1
• '1' during field number 2
V-bit:
• '1' during field blanking
• '0' else
H-bit:
• '0' in sequence SAV
• '1' in sequence EAV
Bits [3:0] (P3..P0) are protection bits. The value of those bits depends on bits F, V and H.
Table 2-3: Definition of SAV, EAV and protection bits
fixed
1
1
1
1
1
1
1
1
F
0
0
0
0
1
1
1
1
SAV/EAV
V
H
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
P3
0
1
1
0
0
1
1
0
protection bits
P2
P1
0
0
1
0
0
1
1
1
1
1
0
1
1
0
0
0
P0
0
1
1
0
1
0
0
1
The VIC implements an error detection and correction based on protection bits. It is possible to detect two-
bit-errors and to correct one-bit-errors.
In case of a two-bit-error the controller takes F- and V-bit directly from current TRC (without error correc-
tion) and inverts H-bit received from previous TRC.
2.3.3 External-Timing-mode
The External-Timing-Mode is only available for MB87P2020-A (Jasmine).
External-Timing-mode is together with VIC windowing function (Register: VICLIMEN) a generalized
Videoscaler-Mode. It is able to receive a horizontal synchronization signal (HSYNC) and a vertical syn-
chronization signal (VSYNC) which is provided by many video devices. Note that the data has to be one of
the formats described in chapter 2.1.
Polarities can be controlled by register EXTPCTRL. Control signal (HSYNC, [pin VSC_VACT], VSYNC,
[pin VSC_VREF] and PARITY [pin VSC_IDENT]) will be taken directly from input.
The HSYNC-pulse tags the begin of a new line and the VSYNC-pulse the begin of a new field/frame. Active
video needs not to be indicated additionally. The start and length of the visible window should be controlled
by windowing function for both dimensions.
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