MB87P2020 Datasheet, PDF (29/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

1 Functional Description
Clock Unit
1.1 Overview
The clock unit (CU) provides all necessary clocks to GDC modules and an own interface to host MCU
(MB91360 series) in order to have durable access even if ULB clocks switched off.
The main functions of CU are:
• Clock source select (Oscillator, MCU Bus clock, Display clock and a reserve clock input)
• Programmable clock muliplier with APLL
• Separate dividers for master (core) clock and pixel clock
• Power management for all GDC modules
• Generation of synchronized RESET signal
• MB91360 series compliant (ULB) Bus interface for clock setup
Figure 1-1 shows the overview of the Clock Unit. OSC_IN, DIS_PIXCLK, ULB_CLK and RCLK¹ are pos-
sible to use as input sources. Both clock outputs of the main unit (MASTERCLK and PIXELCLK) and two
directly used clock inputs (ULB_CLK and VSC_CLKV) driving the clock gates unit which distributes to
all connected GDC sub-modules.
ULB
_A
_RDX
_WRX
_CSX
_CLK
Address Decoder
RSTX
Clk[Con|Pd]R_[rd|wr]
Main Unit
ULB
_D
_A
_WRX
_CLK
Register Set
RSTX
ClkConR
LOCK
ClkPdR
[11]
RSTX
[15]
SW_RST
OSC_IN
ULB_CLK _{Reset Generator}
RESETX
SYNC_RSTX_CU
SYNC_RSTX
Figure 1-1: Block diagram of Clock Unit
MASTERCLK
PIXELCLK
Clock Gates
PE_CLKK_OUT
MAU_CLKK_OUT
MCP_CLK_KOUT
PP_CLKK_OUT
AAF_CLKK_OUT
DIPA_CLKK_OUT
VIS_CLKK_OUT
VIS_CLKV_OUT
SDC_CLKK_OUT
CCFL_CLKK_OUT
SPB_CLKM_OUT
ULB_CLK_OUT
ULB_CLKM_OUT
GPUF_CLKK_OUT
GPUM_CLKK_OUT
GPUB_CLKK_OUT
PIX_CLKD_OUT
SPB_CLKMX_OUT
ULB_CLKKX_OUT
ULB_CLKMX_OUT
1. MODE[3] pin is used for RCLK at Lavender
Functional Description
Page 29