MB87P2020 Datasheet, PDF (342/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

MB87J2120, MB87P2020-A Hardware Manual
Table 2-4: Overview for GPU mastertiming
Subject
Description
Classification
HW limitation
Effects without
workaround
A wrong output picture is visible. Only a hardware reset can solve this
problem.
Solution/Workaround
No asynchronous display clock should be used for Lavender. Core and dis-
play clock should have the same clock source^a.
For Jasmine this problem is solved.
Concerned devices
MB87J2120 (Lavender)
fixed for MB87P2020 (Jasmine)
fixed for MB87P2020-A (Jasmine redesign)
Testcase
EMDC: GPU-P10
a. As common input clock the pins OSC_IN, ULB_CLK, DIS_PIXCLK or RCLK/MODE[3] can be used.
2.4 Read limitation for 16 Bit data interface to MCU
The User Logic Bus interface of MB87J2120 to MB91xxxx MCUs has read limitations in 16Bit data mode
(Pin MODE[2]=0). Read access in 32-Bit data mode (Pin MODE[2]=1) is fully functional as also write ac-
cesses in all modes and access types. Writing to registers works with all modes properly.
This read limitation affects only half word (16 Bit) and byte (8 Bit) read access to Lavender internal regis-
ters (address range 0x0000-0xFBFF) in register space and direct SDRAM read access. It does not affect a
word (32 Bit) read access. In this case the MCU splits the word into two half words (16 Bit) which are sub-
mitted sequentially. For this transmission the order has to be MSB first (Big Endian format). Table 2-5 gives
an overview on all possible modes and read access types.
Table 2-5: Overview for read accesses in different modes
Read access
Mode
Word access
(32Bit)
Halfword access
(16Bit)
32Bit mode read
(MODE[2]=1)
supported
supported
16Bit mode read
(MODE[2]=0)
supported^a
not supported for
offset 2
a. since MCU delivers data in Big Endian order (MSB first).
Byte access
(8Bit)
supported
not supported for
offset 2 and 3
An access to address offset 2 or 3 may lead to delivery of wrong values, depending on address of previous
read access.Figure 2-1 shows these offsets relative to a given address (addr0, addr1) in byte addressed MCU
memory space. The right part of the figure shows the mapping from this memory to internal 32 Bit registers.
There is a possible work-around because reading from an address with offset 0 or 1 to an aligned word ad-
dress (divisible by 4) is fully operable. After the access to an address with offset 0 or 1, read access from
offset 2 or 3 is possible and delivers correct data. If not otherwise guaranteed, a dummy read access on offset
0 or 1 should be included before reading from offset 2 or 3 in order to prepare the correct internal read se-
quence and deliver correct values also for offsets 2 and 3.¹ Alternative to the described procedure read ac-
cesses can be limited to 32-Bit accesses only (see table 2-5).
1. Make sure that this sequence is not interrupted by other read accesses (for instance by an interrupt request
with flag read access).
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