MB87P2020 Datasheet, PDF (65/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

User Logic Bus
1.7.2.1 Level triggered DMA (demand mode)
In case 1. the length of the DREQ signal defines the amount of data to be transferred.
From MCU point of view an external device has to control the length of DREQ impulses according to inter-
nal buffer sizes. It is responsible for the division of data stream while the MCU is only controlling the total
amount of data to be transferred. In the special case of Lavender/Jasmine does this mean that the GDC-
DMAC counts the amount of free words for input FIFO (write DMA) or the number of words in output
FIFO (read DMA). Table 1-14 gives an overview on transfer sizes in different modes for display controller.
Before starting a demand transfer the GDC-DMAC tests for DMA start condition¹, detects the number of
words to be transferred, loads a counter with this value and counts this counter to zero. During counting
ULB_DREQ is set to active. This procedure is repeated until DMA within display controller is disabled.
The GDC-DMAC does not know the total amount of words to be transferred. It only tries to fill (write
DMA) or to flush (read DMA) its FIFOs. At the end of a complete DMA transfer ULB_DREQ could still be
active because from display controller’s point of view DMA is enabled and input FIFO needs data or output
FIFO has to deliver data. After disabling DMA for display controller the ULB_DREQ signal goes inactive.
Figure 1-15 shows the start of a write DMA demand transfer. Display controller requests one input FIFO
Figure 1-15: Write DMA in demand mode
fill cycle². During this time a display controller command is active and reads data from input FIFO concur-
rently. After a short break the second fill cycle is requested.
1.7.2.2 Edge triggered DMA (block-,step-, burstmode)
In case 2. (edge triggered DMA transfer) only the rising edge of ULB_DREQ signal is important. The
amount of data to be transferred is set within MCU (see also table 1-14).
A MCU peripheral device has to ensure that the ULB_DREQ impulse is long enough to be recognized by
MCU. In case of GDC the ULB_DREQ signal goes inactive after the MCU has acknowledged the DMA re-
quest³. Depending on MCU mode (block-, step- or burstmode) a MCU defined amount of data words is
transferred to or from display controller FIFOs. The programmer has to ensure that no FIFO overflow can
occur by setting up the appropriate value for input FIFO lower limit (IFDMA_LL) or output FIFO upper
limit (OFDMA_UL) (see chapter 1.7.3 for a detailed description).
Figure 1-16 shows a write DMA transfer in block mode. The block size is set to 10 words. Despite of this
Jasmine⁴ toggles the ULB_DREQ signal after every falling edge of ULB_DACK signal because it does not
know the MCU settings. It can not distinguish between block-, step- or burst mode.
1. For write DMA: IFDMA_LL >= input FIFO load; for read DMA: OFDMA_UL <= output FIFO load.
2. For Jasmine one complete fill cycle contains 64 words.
3. This is the first high to low edge of the ULB_DACK signal combined with a valid chip select signal.
4. Lavender shows the same behaviour but this example was made with Jasmine.
Functional description
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