MB87P2020 Datasheet, PDF (81/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

SDRAM Controller
1.5 Address Mapping
This section describes the relationship between logical and physical addresses and how to map from a given
logical address to the physical memory position. At the begin we have to introduce the meaning of the used
Layer Description Record (LDR) information. The Address Unit uses the parameters of the 16 LDR entries:
• PHA(i)
Physical Address Offset
• DSZ_X(i)
Domain Size X
• CSPC_CSC(i) Color Space Code.
The address offset PHA, stored in the LDR, describes the start address of a layers position. This is where the
most upper left pixel of a picture is located. Due to the block structure of the picture data, only the part of
the row address is valid for the physical start address offset entry (bits [22:12] for Lavender or [19:10] for
Jasmine, see figure 1-3). Lower bits are fixed to ’0’. That restriction applies because of the same row can’t
be used for different layers. Domain size in X-dimension DSZ_X is given in logical pixels. It is needed to
calculate the pixels per line. The Y-dimension is not needed, there is no automatic layer size limitation im-
plemented. Please note that there is no DSZ_Y register implemented. Color space code CSPC_CSC is a rep-
resentation of the appropriate color format. It is converted internally to calculate the bits per pixel (bpp) by
power of two, which is equal to the number of bits the pixel address has to be shifted to get the right word
address.
Table 1-5: Color Space Codes
Code
Color Space Type
bpp
Shift
0x0
1bpp
1
0
0x1
2bpp
2
1
0x2
4bpp
4
2
0x3
8bpp
8
3
0x4
RGB555
16
4
0x5
RGB565
16
4
0x6
RGB888
32
5
0x7
YUV422
16
4
0x8
YUV444
32
5
0x9-0xD reserved for GPU intermediate color space
0xE
YUV555^a
0xF
YUV656^a
16
5
16
5
a.Jasmine only
The physical address is a combination of SDRAM bank, row and column address. The significance is pre-
defined in following order from row over bank to column address. Thus the picture data is stored in a block-
ing structure drawn in section 1.5.1, figures 1-6/1-7. Additional to physical word addressing there can be
distinguished between several byte addresses. The complete physical address format is shown in figures 1-
Function Description
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