MB87P2020 Datasheet, PDF (85/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

SDRAM Controller
These Commands have it’s dedicated coordinate registers. No address information is fed through Input
FIFO. They are using XYMIN, XYMAX, PPCMD_LAY registers.
Co0^lumn ...
7 0 ... 7
Word
00
08
...
0
1
2
3
ROW
ROW
ROW
ROW
......
n
ROW
F8
00
...
ROnW+1
ROnW+2
......
RO2Wn
F8
...
Figure 1-7: Memory Mapping of Row and Column Address (Jasmine)
• Direct memory mapped Physical Access (DPA)
Command Interface is not necessary for this access method. However some specialities should kept in con-
sideration while using the DPA interface.
— DIPA clock is enabled
— DPA should be enabled by setting SDFLAG to ’1’
— Two windows are possible to map into MCU address space (shares GDC Chip Select)
— Window address offset WNDOF and size WNDSZ are mapped to required address space
— WNDSD is set to the section start address of video RAM which appears in the window
Mapped address calculates to
PHY_MAP = CS_REGION + WNDOF - WNDSD.
WNDSZ limits size of accessible address range. If exceeded no write permission is granted and tri-state
buffers kept close at reading.
DPA runs completely unbuffered. Additional there are no real-time or preferred data channels to the video
RAM available, the normal SDC requesting and arbitration procedures apply. The normal case is that DPA
Function Description
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