MB87P2020 Datasheet, PDF (71/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

2 ULB register set
User Logic Bus
2.1 Description
Some ULB registers are controlled by ULB itself and some are handled by CTRL in the same manner as
for all other GDC components. For the programmer there is no difference accessing these registers. An
overview on ULB- and CTRL controlled registers has already been given in table 1-5, section 1.4.
In table 2-1 an overview on all ULB registers is given. All addresses are relative to start of register space
for given GDC; see section 1.4 for details. The address values are byte addresses and can be accessed in
word (32 Bit), halfword (16 Bit) or byte (8 Bit) mode from MCU, except the FIFOs which can only be ac-
cessed in word mode.
Flag and interrupt mask register handling:
As already mentioned in section 1.6 the ULB contains one flag- and one interrupt mask register with special
access modes; therefore in table 2-1 flag- and interrupt mask register have each three addresses.
Register
Name
Address
CMD
0x0000
IFIFO
OFIFO
FLNOM
FLRST
FLSET
0x0004
0x0008
0x000C
0x0010
0x0014
INTNOM
0x0018
INTRST 0x001C
INTSET
0x0020
INTLVL
0x0024
WNDOF0
WNDSZ0
0x0040
0x0044
Table 2-1: ULB register description
Bits Group
Name
Description
Default value
31:8 PAR
7:0 CODE
31:0 -
31:0 -
31:0 ^-
31:0 ^-
31:0 ^-
-
31:0
-
31:0
31:0 ^-
31:0
20:0 OFF
20:0 SIZE
Command parameter
0
Command code
0xFF (NoOp)
Input FIFO
-
Output FIFO
-
Flag register (normal write access)^{a 0x20400000}
Flag register (reset write access)^a
0x20400000
Flag register (set write access)^a
0x20400000
Interrupt mask register (normal
write access)
0
’1’: use flag for interrupt
Interrupt mask register (reset write
access)
0
’1’: use flag for interrupt
Interrupt mask register (set write
access)
0
Interrupt level/edge settings
’1’: positive edge of flag triggers
interrupt^b
’0’: high level of flag triggers inter-
rupt
0xFFFFFFFF
MCU offset for SDRAM window 0 0x10000
Size of SDRAM window 0
0x20000
ULB register set
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