MB87P2020 Datasheet, PDF (185/356 Pages) Fujitsu Component Limited. – Colour LCD/CRT/TV Controller

Graphic Processing Unit
Table 3-15: GPU sync signal to GDC pin assignment.
GDC pin
GPU signal usage
DIS_VSYNC This pin is always connected to the delay adjusted output of Sync Mixer 1.
DIS_VREF This pin is always connected to the delay adjusted output of Sync Mixer 2.
Note: Although the pin names seem to imply a certain signal function this is not the case. In fact, any of
the pins above can output any arbitrary waveform generated with the respective Sync Mixer.
3.14.4 Sync Mixer connections
Table 3-16 shows the mapping of sync mixer outputs to GDC pins or its internal connections.
Table 3-16: Sync mixer connections
Sync mixer
Sync mixer 0
Sync mixer 1
Sync mixer 2
Sync mixer 3
Sync mixer 4
Sync mixer 5
Sync mixer 6
Sync mixer 7
GDC pin
DIS_HSYNC
DIS_VSYNC
DIS_VREF
DIS_D[19]
DIS_D[20]
DIS_D[21]
DIS_D[22]
DIS_D[23]
Internal connection
CCFL synchronization (MB87P2020-A only)
Flag FLNOM_GSYNC (MB87P2020(-A) only)
Clock gating
Sync mixer 7 is used for pixel clock gating as already described in chapter 3.11.
Sync mixer 6 is connected to the flag FLNOM_GSYNC which can be used by an application to trigger on an
event regarding display output. For example with help of this flag an application can synchronize its draw-
ing on display frame rate. It is also possible to generate a MCU interrupt with this flag (see ULB description
for details about flags and interrupt handling).
Note that this connection is only available for MB87P2020 and MB87P2020-A.
Sync mixer 5 can be taken as synchronization input for the CCFL driver. This allows a flexible CCFL flash
rate synchronization with display output refresh rate. See CCFL description for further details about syn-
chronization settings.
Note that this connection is only available for MB87P2020-A.
Internal connections for sync mixers are always established independent from display settings.
3.14.5 Color Key Output
The GDC pin DIS_CK carries the output of the color key unit. It is high-Z when the respective output enable
bit is reset.
Behaviour:
The output becomes active with a user-controlled polarity when data for visible pixels is output that lies
within limits that are also defined by the user. It is inactive during blanking periods. The behaviour further
depends on physical color space / bit stream format combinations:
• For combinations that lead to an output of one pixel per pixel clock, the output is updated on a per-
pixel basis.
GPU Control Information
Page 185