MC68HC908LD64 Datasheet, PDF (51/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Memory Map
Input/Output (I/O) Section
Addr. Register Name
Bit 7
6
$003C
Read: AD7
AD6
ADC Data Register
(ADR)
Write:
Reset:
Read:
$003D
ADC Input Clock Register
(ADICLK)
Write:
Reset:
ADIV2
0
ADIV1
0
Read:
$003E
Unimplemented Write:
Reset:
H & V Sync Output Control ^Read:
$003F
Register Write:
(HVOCR) _Reset:
Sync Processor Control ^Read: _VSIE
$0040
and Status Register Write:
(SPCSR) _{Reset: 0}
VEDGE
0
Vertical Frequency High ^{Read: VOF}
$0041
Register Write:
(VFHR) _{Reset: 0}
0
CPW1
0
Vertical Frequency Low ^{Read: VF7}
VF6
$0042
Register Write:
(VFLR) _{Reset: 0}
0
$0043
Hsync Frequency High ^Read:
Register Write:
(HFHR) _Reset:
HFH7
0
HFH6
0
Hsync Frequency Low ^{Read: HOVER}
0
$0044
Register Write:
(HFLR) _{Reset: 0}
0
Sync Processor I/O Control ^{Read: VSYNCS}
$0045
Register Write:
(SPIOCR) _{Reset: 0}
HSYNCS
0
5
4
3
2
AD5
AD4
AD3
AD2
Indeterminate after reset
0
0
0
ADIV0
0
0
0
0
DCLKPH1 DCLKPH0 R
VSIF
0
0
0
CPW0
0
VF5
0
COMP
0
VF12
0
VF4
0
VINVO
0
VF11
0
VF3
HINVO
0
VF10
0
VF2
0
HFH5
0
HFH4
0
HFH3
0
HFH2
0
0
0
0
0
HFL4 HFL3 HFL2
0
0
0
0
COINV
R
R
R
0
1
Bit 0
AD1
AD0
0
0
0
0
HVOCR1 HVOCR0
0
VPOL
0
HPOL
0
0
VF9
VF8
0
0
VF1
VF0
0
HFH1
0
HFH0
0
HFL1
0
HFL0
0
BPOR
0
0
SOUT
0
U = Unaffected
X = Indeterminate
= Unimplemented
R = Reserved
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 15)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Memory Map
Data Sheet
51