MC68HC908LD64 Datasheet, PDF (243/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

DDC12AB Interface
DDC Registers
BR2–BR0 — Baud Rate Select
These three bits select one of eight clock rates as the master clock
when the module is in master mode.
Since this master clock is derived the CPU bus clock, the user
program should not execute the WAIT instruction when the DDC
module in master mode. This will cause the SDA and SCL lines to
hang, as the WAIT instruction places the MCU in wait mode, with CPU
clock is halted. These bits are cleared upon reset. (See Table 16-2 .
Baud Rate Select.)
Table 16-2. Baud Rate Select
BR2
BR1
BR0
Baud Rate
0
0
0
100 k
0
0
1
50 k
0
1
0
25 k
0
1
1
12.5 k
1
0
0
6.25 k
1
0
1
3.125 k
1
1
0
1.56 k
1
1
1
0.78 k
NOTE:
CPU bus clock is external clock ÷ 4 = 6MHz
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
DDC12AB Interface
Data Sheet
243