MC68HC908LD64 Datasheet, PDF (299/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
Port A
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 19-2 summarizes
the operation of the port A pins.
Table 19-2. Port A Pin Functions
DDRA
Bit
0
PTA Bit
X⁽¹⁾
I/O Pin Mode
Input, Hi-Z⁽²⁾
Accesses to DDRA
Read/Write
DDRA[7:0]
1
X
Output
DDRA[7:0]
Notes:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
Accesses to PTA
Read
Pin
Write
PTA[7:0]⁽³⁾
PTA[7:0] PTA[7:0]
19.3.3 Port A Options
The keyboard interrupt enable register (KBIER) selects the port A pins
for keyboard interrupt function or as standard I/O function. (See Section
21. Keyboard Interrupt Module (KBI).)
Address: $004F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
KBIE7
Write:
KBIE6
KBIE5
KBIE4
KBIE3
KBIE2
KBIE1
KBIE0
Reset: 0
0
0
0
0
0
0
0
Figure 19-5. Keyboard Interrupt Enable Register (KIER)
KBIE[7:0] — Keyboard Interrupt Enable Bits
Setting a KBIEx bit to logic 1 configures the PTAx/KBIx pin for
keyboard interrupt function. Reset clears the KBIEx bits.
1 = PTAx/KBIx pin configured as KBIx interrupt pin
0 = PTAx/KBIx pin configured as PTAx standard I/O pin
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Input/Output (I/O) Ports
Data Sheet
299