MC68HC908LD64 Datasheet, PDF (111/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

8.7 Interrupts
Clock Generator Module (CGM)
Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,
becomes set whether interrupts are enabled or not. When the AUTO bit
is clear, CPU interrupts from the PLL are disabled and PLLF reads as 0.
Software should read the LOCK bit after a PLL interrupt request to see
if the request was due to an entry into lock or an exit from lock. When the
PLL enters lock, the VCO clock CGMVCLK, can be selected as the
DCLK1 source by setting BCS in the PCTL. When the PLL exits lock, the
VCO clock frequency is corrupt, and appropriate precautions should be
taken. If the application is not frequency-sensitive, interrupts should be
disabled to prevent PLL interrupt service routines from impeding
software performance or from exceeding stack limitations.
Software can select CGMVCLK as the DCLK1 source even if the PLL is
not locked (LOCK = 0). Therefore, software should make sure the PLL
is locked before setting the BCS bit.
8.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power-
consumption standby modes.
8.8.1 Wait Mode
The WAIT instruction does not affect the CGM. Before entering WAIT
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from WAIT mode also can
deselect the PLL output without turning off the PLL.
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor
Clock Generator Module (CGM)
Data Sheet
111