MC68HC908LD64 Datasheet, PDF (110/362 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
8.6.4 H & V Sync Output Control Register (HVOCR)
The H&V sync output control register controls the PLL reference input
prescaler and the final free-running waveforms for the sync processor
output signals on HOUT, VOUT, DCLK, and DE pins.
(See Section 17. Sync Processor.)
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
DCLKPH1 DCLKPH0 R HVOCR1 HVOCR0
Reset:
0
0
0
0
= Unimplemented
R = Reserved
Figure 8-6. H&V Sync Output Control Register (HVOCR)
DCLKPH[1:0] — DCLK Output Phase Adjustment
These two bits are programmed to adjust the DCLK output phase.
Each increment adds approximately 2 to 3ns delay to the DCLK output.
HVOCR[1:0] — Free Running Video Mode Select Bits
These two bits together with MUL[7:4] and VRS[7:4] in the PLL
programming register determine the frequencies of the internal
generated free-running signals for output to HOUT, VOUT, DE, and
DCLK pins, when the SOUT bit is set in the sync processor I/O control
register. These two bits determine the prescaler of PLL reference
clock in the CGM module. When HVOCR[1:0]=11, the prescaler is 2;
for other values, the prescaler is 3. Reset clears these bits, setting a
default horizontal frequency of 31.25kHz and a vertical frequency of
60Hz, a video mode of 640×480.
Register Settings
HVOCR[1:0] MUL[7:4] VRS[7:4]
00
3
3
01
5
3
10
8
6
11
9
9
Pin Outputs
HOUT
VOUT
DCLK
Frequency Frequency Frequency
31.45kHz 59.91Hz
24 MHz
37.87kHz 60.31Hz
40 MHz
48.37kHz 60.31Hz
64 MHz
64.32kHz 60.00Hz
108 MHz
Video Modes
DE Video Mode
VGA 640 × 480
SVGA 800 × 600
XGA 1024 × 768
SXGA 1280 × 1024
Data Sheet
110
Clock Generator Module (CGM)
MC68HC908LD64 — Rev. 3.0
Freescale Semiconductor